Browsing by Subject "ADC"
Now showing 1 - 20 of 20
- Results Per Page
- Sort Options
Item Application specific DAC and ADC for a bio-impedance measurement circuit(2017-06-22) Rajendran, Kaarthik; Valvano, Jonathan W., 1953-A transistor level implementation of a 3 bit digital harmonic canceling (DHC) digital to analog converter (DAC), and a 10 bit successive approximation register (SAR) analog to digital converter (ADC) is designed. The circuits are intended to be a part of a bio-impedance measurement system in which a current is injected into the myocardium tissue and blood pool for the purpose of determining the heart’s stroke volume. The DHC DAC injects a 100 μA[subscript rms] current at a 20 kHz fundamental frequency using appropriately weighted current mirrors from a 160 kHz square-wave reference clock. A [function subscript s] = 160 kS/s ADC is designed with synchronous SAR logic, bottom-plate sampling, and a charge-redistribution capacitive DAC.Item An attitude determination and control system for small satellites(2015-05) Tam, Margaret Hoi Ting; Fowler, Wallace T.; Lightsey, E. GlennA flexible, robust attitude determination and control (ADC) system is presented for small satellite platforms. Using commercial-off-the-shelf sensors, reaction wheels, and magnetorquers which fit within the 3U CubeSat form factor, the system delivers arc-minute pointing precision. The ADC system includes a multiplicative extended Kalman filter for attitude determination and a slew rate controller that acquires a view of the Sun for navigation purposes. A pointing system is developed that includes a choice of two pointing controllers -- a proportional derivative controller and a nonlinear sliding mode controller. This system can reorient the spacecraft to satisfy a variety of mission objectives, but it does not enforce attitude constraints. A constrained attitude guidance system that can enforce an arbitrary set of attitude constraints is then proposed as an improvement upon the unconstrained pointing system. The momentum stored by the reaction wheels is managed using magnetorquers to prevent wheel saturation. The system was thoroughly tested in realistic software- and hardware-in-the-loop simulations that included environmental disturbances, parameter uncertainty, actuator dynamics, and sensor bias and noise.Item Circuit techniques for programmable broadband radio receivers(2013-12) Forbes, Travis Michael, 1986-; Gharpurey, RanjitThe functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF.Item Circuits and architectures for broadband radio receivers and spectrum channelizers(2017-12-08) Singh, Vineet Kumar; Gharpurey, Ranjit; Orshansky, Michael; Sun, Nan; Akinwande, Deji; Pullela, RajaA broadband spectrum channelizer divides the spectrum of an input signal into sub-bands prior to baseband processing. Efficient spectrum channelizer architectures can serve as enablers for new systems and applications for communications, signal analysis and detection. Channelizers can be used to implement broadband receivers for mobile applications, that are capable of receiving signals corresponding to multiple standards, and general-purpose hybrid frequency-and-time domain analog to digital converters (ADCs). These designs can help to relax baseband design specifications, and can also be more spectrum-aware than a broadband direct-sampling ADC front-end. Circuits and architectures for the implementation of broadband spectrum channelizers are proposed in this research. First, a channelizing broadband receiver that employs a bank of two-stage harmonic rejection mixers (HRMs) is described. Each HRM internally synthesizes a distinct downconversion LO, while using a fixed high-frequency master clock. The HRMs also implement a quadrature phase matching technique for enhancing image rejection. The technique counters the impact of transistor mismatches on the phase matching between quadrature paths. This reduces the two-dimensional calibration for enhancing image performance, that requires amplitude and phase correction, into a one-dimensional problem, thereby significantly reducing calibration complexity. A prototype receiver employing this principle has been implemented in a 65nm CMOS process. The design down-converts an I/Q input of bandwidth 250 MHz to baseband and channelizes the signal concurrently into 16 sub-bands of bandwidth 15.625 MHz each. It achieves an image rejection of 56 dB with amplitude calibration alone, and a harmonic rejection of 56.5 dB without any calibration at a 1 MHz baseband output. Second, a frequency-folding channelizer architecture is proposed, which can span bandwidths of several GHz. A digital post-processing approach for reducing the anti-aliasing requirement is described. A signal of bandwidth (N/2)f [subscript LO] is downconverted into N paths that are clocked using rectangular, non-overlapping pulse waveforms at a fundamental frequency of f [subscript LO] with a duty-cycle of 1/N. All parts of the input are aliased onto a baseband signal of bandwidth f [subscript LO]/2, which is low-pass filtered and applied to an ADC, where each path employs identical sampling clocks. A digital equalization technique is presented that can be utilized to recover the complete broadband input, similar to a high-speed ADC, or recover each channelized and down-converted sub-band, similar to a bank of mixers, while performing digital-domain harmonic and image rejection. Aliasing can be reversed through equalization and this is used to reduce the order of the anti-aliasing filters in the analog signal paths, potentially reducing power requirement and design complexity. A theoretical and simulation-based analysis of channelizer performance after signal reconstruction is presented. Impact of filter-order on SNR affected by noise and impairments is also analyzed. The equalization technique is analyzed in the context of a previously reported channelizer IC. It is shown that the application of the equalization can result in 50 dB broadband SNR over 1 GHz input bandwidth, using 8 paths with 3rd-order anti-aliasing analog filters and 10-bit sub-ADCs.Item Clinica de Derechos Humanos Universidad de Texas, March 23, 2011(2011-03-23) Osorio, Jessica; Alvarez Ugarte, RamiroItem Design of a time-based sigma-delta modulator(2010-08) Dutta, Arnab Kumar, 1984-; Hassibi, Arjang; Swanson, EricIn this thesis, a time-based oversampling sigma-delta analog-to-digital converter (ADC) architecture is introduced. This system uses time, instead of voltage, as the analog variable for it quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital pulse. The sigma-delta loop integrator, comparator, and subtractor are all time-based circuits and implemented by using only digital gates. The only voltage-based circuit is voltage-to-time Converter (VTC) which requires only a current source. No amplifier is required in the entire circuit. As a proof of concept, the simulation results for a prototype ADC incorporating this time-based sigma-delta ADC architecture is presented.Item Design techniques for low-power SAR ADCs in nano-scale CMOS technologies(2016-05) Chen, Long; Sun, Nan; Viswanathan, T.R.; Pan, David Z.; Orshansky, Michael; Soenen, EricThis thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. To improve the comparator’s power efficiency, a statistical estimation based comparator noise reduction technique is presented. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR) by estimating the conversion residue. A first prototype ADC in 65nm CMOS has been developed to validate the proposed noise reduction technique. It achieves 4.5 fJ/conv-step Walden figure of merit and 64.5 dB signal-to-noise and distortion ratio (SNDR). In addition, a bidirectional single-side switching technique is developed to reduce the DAC switching power. It can reduce the DAC switching power and the total number of unit capacitors by 86% and 75%, respectively. A second prototype ADC with the proposed switching technique is designed and fabricated in 180nm CMOS technology. It achieves an SNDR of 63.4 dB and consumes only 24 Wat 1MS/s, leading to aWalden figure of merit of 19.9 fJ/conv-step. This thesis also presents an improved loop-unrolled SAR ADC, which works at high frequency with reduced SAR logic power and delay. It employs the bidirectional single-side switching technique to reduce the comparator common-mode voltage variation. In addition, it uses a Vcm-adaptive offset calibration technique which can accurately calibrate comparator’s offset at its operating Vcm. A prototype ADC designed in 40nm CMOS achieves 35 dB at 700 MS/s sampling rate and consumes only 0.95 mW, leading to a Walden figure of merit of 30 fJ/conv-step.Item Direct sampling receivers for broadband communications(2018-12) Fang, Jie, (Ph. D.); Abraham, Jacob A.; Gharpurey, Ranjit; Orshansky, Michael; Sun, Nan; Li, ZhiminToday everything tends to be connected in the Internet of Things (IoT) universe, where a broad variety of communication standards and technologies are used for those connected devices. It is always a dream to design a Software-Defined Radio (SDR) supporting different standards solely based on the software configuration. As integrated-circuit (IC) manufacture and design advance, a partial of SDR can be realized. This thesis investigates one of the most important parts in a SDR: the analog design of a direct sampling (DS) receiver, which mainly consists of a broadband RF front end and a wideband ADC. Especially, a DS receiver shows a great flexibility and efficiency for the simultaneous reception of multiple channels comparing with the traditional parallelism of superheterodyne structure. The research contributions of this work include (1) demonstration and comparative analysis of two new architectures of broadband RFPGAs: voltage-mode: RFPGA-V and current-mode: RFPGA-I. RFPGA-V and RFPGA-I utilize an innovative interpolation method and current steering approach, respectively, to achieve a fine gain step of 0.25-dB over 40-dB gain range for several GHz frequency range. Besides, with innovative design, no off-chip inductor is needed for the both RFPGAs. (2) The design of a 5-GS/s 10b time-interleaved SAR. The ADC power efficiency is significantly improved by many design techniques: the low-energy CDAC switching scheme, optimized input common-mode voltage for comparator, optimal reduced radix-2 capacitor ratio for low-power reference buffers and higher conversion speed, etc. The lane-to-lane mismatches in a time-interleave ADC are minimized by using optimal floor plan and then are calibrated digitally. Three prototypes: the broadband RF front ends with RFPGA-V, the broadband RF front ends with RFPGA-I and a 5-GHz ADC, are fabricated to verify the proposed ideas in 28nm CMOS technology.Item Energy-efficient data converter design in scaled CMOS technology(2019-08) Tang, Xiyuan; Sun, Nan; Pan, David Z.; Orshansky, Michael; Khoury, John; Thomsen, AxelData converters bridge the physical and digital worlds. They have been the crucial building blocks in modern electronic systems, and are expected to have a growing significance in the booming era of Internet-of-Things (IoT) and 5G communications. The applications raise energy-efficiency requirements for both low-speed and high-speed converters since they are widely deployed in wireless sensor nodes and portable devices. To explore the solutions, the author worked on three directions: 1) techniques to improve the efficiency of the low-speed converters including the comparator; 2) techniques to develop high-speed data converters including the reference stabilization; 3) new architecture to improve the efficiency of the capacitance-to-digital converter (CDC). In the first part, a power-efficient 10-bit SAR ADC featured with a gain-boosted dynamic comparator is presented. In energy-constrained applications, the converter is usually supplied with low supply voltage (e.g., 0.3 V-0.5 V), which reduces the comparator pre-amplifier (pre-amp) gain and results in higher noise. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain, thereby reducing noise and offset. Besides, statistical estimation and loading switching techniques are combined to further improve energy efficiency. A 40-nm CMOS prototype achieves a Walden FoM of 1.5 fJ/conversion-step while operating at 100-kS/s from a 0.5-V supply. To further improve the energy-efficiency of the comparator, a novel dynamic pre-amp is proposed. By using an inverter-based input pair powered by a floating reservoir capacitor, the pre-amp realizes both current reuse and dynamic bias, thereby significantly boosting g [subscript m] /I [subscript D] and reducing noise. Moreover, it greatly reduces the influence of the input common-mode (CM) voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180-nm achieves 46-μV input-referred noise while consuming only 1 pJ per comparison under 1.2-V supply, which represents greater than 7 times energy efficiency boost compared to that of a Strong-Arm (SA) latch. The second part of this dissertation focuses on high-speed data converter techniques. A 10-bit high-speed two-stage loop-unrolled SAR ADC is presented. To reduce the SAR logic delay and power, each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. To suppress the comparator offset mismatch induced non-linearity, a shared pre-amp are employed in the second fine stage, which is implemented by a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55-dB peak SNDR at 200-MS/s sampling rate without any calibration. A key limiting factor for the SAR ADC to simultaneously achieve high speed and high resolution is the reference ripple settling problem caused by DAC switching. Unlike prior techniques that aim to minimize the reference ripple which requires large reference buffer power or on-chip decoupling capacitance area, this work proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. The prototype 10-bit 120-MS/s SAR ADC is fabricated in 40-nm CMOS process and achieves an SNDR of 55 dB with only 3 pF reference decoupling capacitor. Finally, this dissertation also presents the design of an incremental time-domain two-step CDC. Unlike the classic two-step CDC, this work replaces the OTA-based active-RC integrator with a VCO-based integrator and performs time domain (TD) ΔΣ modulation. The VCO is mostly digital and consumes low power. Featuring the infinite DC gain in phase domain and intrinsic spatial phase quantization, this TDΔΣ enables a CDC design, achieving 85-dB SQNR by having only a 4-bit quantizer, a 1st-order loop and a low OSR of 15. The prototype fabricated in 40-nm CMOS achieves a resolution of 0.29 fF while dissipating only 0.083 nJ per conversion, which improves the energy efficiency by greater than 2 times comparing to that of state-of-the-art CDCsItem Integrated temperature sensors in deep sub-micron CMOS technologies(2014-05) Chowdhury, Golam Rasul; Hassibi, ArjangIntegrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.Item Investigation of 10-bit SAR ADC using flip-flip bypass circuit(2013-12) Fontaine, Robert Alexander; Sun, NanThe Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by settling time and control logic constraints. This report investigates a flip-flop bypass technique to reduce the required conversion time. A conventional design and flip-flop bypass design are simulated using a 0.18[micrometer] CMOS process. Background and design of the control logic, comparator, capacitive array, and switches for implementing the SAR ADCs is presented with the emphasis on optimizing for conversion speed.Item Los pedidos que se han hecho, March 23-28, 2011(2011-03-23) Osorio, Jessica; Giorgelli, Maria Julia; Aparicio Soriano, LeticiaItem Low power VCO-based analog-to-digital conversion(2014-05) Gupta, Amit Kumar; Viswanathan, T. R., doctor of electrical engineering; Hassibi, Arjang; Touba, Nur; John, Lizy K; Sun, Nan; Nagaraj, KrishnaswamyThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Item Low-power ADC designs in scaled CMOS process(2017-05) Yoon, Yeonam; Sun, Nan; Viswanathan, TR; Pan, David Z; Orshansky, Michael; Soenen, EricThis thesis presents advanced design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs), continuous-time ∆Σ ADCs, and single-slope (SS) ADCs in nano-scale CMOS technologies. (1) In high-speed SAR ADCs, metastability of the comparator limits the performance, which even results in the sparkle code errors. Proposed background calibration utilizing the comparator decision time detector removes the metastability-induced sparkle code errors by controlling the metastability detection window. At the same time, 1-bit resolution increase is gained from the proposed technique, which results in the fewer comparison cycles. Along with the relaxed requirement on the comparator, this cycle reduction helps to achieve the good power efficiency in high-speed SAR design. A prototype ADC in 40nm CMOS achieves 35.3dB SNDR and consumes 0.81mW while sampling at 700MS/s. (2) In the proposed continuous-time ∆Σ ADCs, conventional power-hungry opamp is replaced by voltage controlled oscillators (VCOs) that perform the data conversion in the phase domain instead of the voltage domain. In contrary to the opamp which is difficult to achieve good performance in the advanced CMOS process, VCOs have many advantages in the phase domain. To solve the nonlinear gain of VCOs, dual VCO-based integrator is used to suppress the dominant second-order distortion. To address the distortion from the DAC, a novel DAC calibration technique that both digitally senses and removes DAC mismatch errors is proposed. It has low hardware complexity by taking advantage of the intrinsic clocked level averaging (CLA) capability of dual-VCO-based integrator. It ensures high linearity regardless of the VCO center frequency. By lowering the VCO center frequency, power consumption is reduced. A prototype ADC designed in 130nm occupies an area of only 0.04mm² . It achieves 71dB SNDR over 1.7MHz bandwidth (BW) while sampling at 250MS/s and consuming only 0.9mW from a 1.2V power supply. The corresponding figure-of-merit (FOM) is 98 fJ/conversion-step. (3) A SS ADC has advantages of high linearity and a simple architecture. Thus, it is well suited for the column-parallel architecture for the CMOS image sensors. However, conversion speed is severely limited in high-bit resolution since more than 2 [superscript N] cycles are required for a N-bit resolution. To tackle this limitation, a two-step approach becomes popular. In this thesis, a two-step SAR/SS architecture is presented. In addition to reducing the conversion time, analog correlated double sampling (CDS) can cancel kT/C noise, which enables capacitor area reduction. A prototype ADC in 180nm CMOS occupies only 9.3µm x 830µm. It achieves 60.5dB SNR after CDS while sampling at 256kHz and consuming 91µWItem Multichannel digital voltmeter using the LM3S8962 evaluation board(2016-08) Muckelroy, Callie Edward; Valvano, Jonathan W., 1953-; Bard, William Carl, 1944-This project is a proof of concept and prototype in both hardware and software, which demonstrates a useful and flexible 4-channel voltmeter using an LM3S8962 Evaluation Board, and commodity electronic components to serve as a shield circuit. The shield circuit protects the evaluation board from over/under voltage damage, and biases the incoming voltages to provide usable input voltages for the LM3S8962 ADC inputs. The report begins with an explanation of the goals of the project, and research of what current products exist on the commercial market to meet the needs of multichannel voltage measurement. In the interest of cost savings, and in the interest of an academic exploration of the capabilities of the inexpensive evaluation boards on the market, the author explores how the ADC inputs of the LM3S8962 can serve some of the same needs of much more expensive commercial products in voltage measurement. Several obstacles were encountered in the design and construction stages. A description of the obstacles, and how they were overcome is described. The end design of both the shield circuit and software is then detailed end-to-end, along with an explanation of how to use the end product. Finally, the accuracy of the project is assessed and demonstrated.Item Noise shaping Asynchronous SAR ADC based time to digital converter(2016-05-03) Katragadda, Sowmya; Sun, Nan; Gharpurey, RanjitTime-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Item Pseudo pipelined SAR ADC with regenerative amplifier(2015-05) Gnana, Anoosh; Sun, Nan; Gharpurey, RanjitThe power consumption of Analog to digital converters (ADCs) is an important design criterion in today’s market of wireless and battery operated stand alone systems. Successive approximation register (SAR) ADCs do very well in this regard and have been designed with excellent figures of merit with respect to power. However, their speeds of operation are low. Pipelined ADCs have been known to do very well where speed and performance are important criteria. There have been multiple works where combinations of the two have been used in order to leverage on the benefits of each. This work explores the different options we have in implementing the residue amplifier in a two stage pipelined ADC. A linear op-amp is traditionally used to implement the residue amplifier. Integrators have been used for this purpose as well. This design takes it one step further and explores the feasibility of using positive feedback amplification in order to achieve the function of the residue amplifier. The challenges and concepts of this new design architecture are explored. A test chip will be fabricated with this design as well and its performance in silicon will be published at a later time.Item System-level design and analysis of an embedded audio signal processing application(2016-05) Dollo, Philippe Marc; Sun, Nan; Akinwande, DejiIn this report, a design is proposed for an embedded system that implements an audio beamforming application. This design provides the key considerations for both the analog front-end, and the digital signal processing that would be included on-chip. The analog portion of the design implements a multi-order delta-sigma ADC, and the digital portion of the design implements a digital decimation filter and a beamforming filter. The objective of the project is to develop a system that could be used in a real-world implementation, with design decisions which attempt to account for system-wide specifications, rather than focusing on block-level performance alone.Item Tunable mismatch shaping for bandpass Delta-Sigma data converters(2011-05) Akram, Waqas; Swartzlander, Earl E.; Driga, Mircea D.; Orshansky, Michael E.; Telang, Vivek; Touba, Nur A.Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between the unit elements, leading to a sharp reduction in the effective dynamic range through the converter. Mismatch noise shaping is an established technique for alleviating these effects, but usually anchors the signal band to a fixed frequency location. In order to extend these advantages to tunable applications, this work explores a series of techniques that allow the suppression band of the mismatch noise shaping function to have an adjustable center frequency. The proposed techniques are implemented in hardware and evaluated according to mismatch shaping performance, latency and hardware complexity.Item VCO-based analog-to-digital conversion(2012-12) Hamilton, Joseph Garrett; Hassibi, Arjang; Viswanathan, T. R., doctor of electrical engineeringThis dissertation presents a novel [delta sigma] analog-to-digital converter architecture which replaces the operational amplifier-based integrator with a pair of tunable oscillators. A switched-capacitor V-I converter is used to combine the input voltage with a feedback DAC output and convert it into a current for two pseudo-differential current-controlled oscillators. The oscillator outputs are counted with a digital counter, and a digital back-end [delta sigma] modulator is used to truncate the high-resolution counter outputs for the feedback DAC path. This architecture has compelling advantages in deep sub-micron and emerging technologies where supply voltages are decreasing to a point that traditional analog architectures are no longer feasible. Additionally, this architecture takes advantage of the increased speed in these short-channel technologies. Measured results on a 6.08mW prototype in TSMC 0.18um achieving 63.5dB in a 2MHz bandwidth are presented.