EDA design for Microscale Modular Assembled ASIC (M2A2) circuits
| dc.contributor.advisor | Sreenivasan, S. V. | |
| dc.contributor.advisor | McDermott, Mark William (Ph. D. in electrical and computer engineering) | |
| dc.creator | Sayal, Aseem | |
| dc.creator.orcid | 0000-0003-3078-9498 | |
| dc.date.accessioned | 2019-11-14T17:22:38Z | |
| dc.date.available | 2019-11-14T17:22:38Z | |
| dc.date.created | 2017-05 | |
| dc.date.issued | 2017-05-05 | |
| dc.date.submitted | May 2017 | |
| dc.date.updated | 2019-11-14T17:22:38Z | |
| dc.description.abstract | As the semiconductor industry has driven down the minimum feature size to well below 50nm, the mask cost to make devices has skyrocketed. The cost for a full set of masks is estimated to be about $1.5M for 90nm node devices and exceeding $2M for 65nm lithography nodes. According to some estimates, mask writing time goes up as a power of five as feature sizes are decreased below 50nm. In addition, higher complexity of large designs increases the number of design re-spins. The above two factors lead to considerable increase in the nonrecurring engineering cost (NRE) for standard cell ASICs, which has become prohibitively expensive for low to mid volume applications. Field programmable gate array (FPGAs) offer an acceptable solution for fast prototyping and ultra-low volume applications, but are generally not seen as a replacement for ASICs because of their highly inefficient space utilization, lower performance/speed and high power consumption. This is particularly the case as mobility has driven expectations for small form factor and low power consumption. In this work, a new type of ASICs named as Microscale Modular Assembled ASIC (M2A2) is proposed. This technology is a novel application of the high-speed, precision assembly technique for fabrication of ASICs using a limited number of mass-produced feedstock logic circuits. The idea is to share the mask cost for sub-100nm feature sizes across a large number of ASIC designs, decreasing the NRE for individual designs. The concept of constructing ASICs using repeating logic elements is based on previous works where it has been shown that ASICs made of via/metal configured structured elements can achieve space utilization and performance comparable to cell based ASICs. However, in the proposed technique, we provide significantly more choice in the transistor layer, in terms of feedstock types and their configuration. This thesis document deals with the electronic design automation (EDA) design for microscale modular assembled ASIC based circuits. The document discusses the design of feedstock cells, generation of feedstock preplaced design, generation of design collaterals to support M2A2 EDA flow, and front end M2A2 synthesis flow to meet the required functionality of design and achieve optimal quality of results (QoR) metrics in terms of circuit performance/speed, power and area | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | https://hdl.handle.net/2152/78394 | |
| dc.identifier.uri | http://dx.doi.org/10.26153/tsw/5481 | |
| dc.language.iso | en | |
| dc.subject | ASIC | |
| dc.subject | Structured ASIC | |
| dc.subject | M2A2 | |
| dc.subject | FPGA | |
| dc.subject | Low volume ASIC | |
| dc.subject | VLSI | |
| dc.title | EDA design for Microscale Modular Assembled ASIC (M2A2) circuits | |
| dc.type | Thesis | |
| dc.type.material | text | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | The University of Texas at Austin | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science in Engineering |