Test and security in a System-on-Chip environment

dc.contributor.advisorTouba, Nur A.
dc.contributor.committeeMemberPan, David
dc.contributor.committeeMemberSwartzlander, Earl
dc.contributor.committeeMemberJohn, Lizy
dc.contributor.committeeMemberHuang, Gang
dc.creatorLee, Yu-Wei
dc.creator.orcid0000-0003-1637-3867
dc.date.accessioned2019-07-30T16:21:35Z
dc.date.available2019-07-30T16:21:35Z
dc.date.created2017-05
dc.date.issued2017-05
dc.date.submittedMay 2017
dc.date.updated2019-07-30T16:21:36Z
dc.description.abstractThis dissertation outlines new approaches for test and security in a System-on-Chip (SoC) environment. A methodology is proposed for designing a single test access mechanism (TAM) architecture on each die with a "bandwidth adapter" that allows it to be efficiently used for multiple different test data bandwidths in three-dimensional integrated circuits (3D-IC) using through-silicon vias (TSVs). In this way, a single test architecture can be re-used for pre-bond, partial stack, and post-bond testing while minimizing test time across all phases of test. Unlike previous approaches, this methodology does not need multiple TAM architectures or reconfigurable wrappers in order to be efficient when the test data bandwidth changes. In industry, sequential linear decompression is widely used to reduce data and bandwidth requirements. A new scheme using a multiple polynomial linear feedback shift register (LFSR) with rotating polynomial is proposed here to increase encoding flexibility resulting in higher compression ratios. An algorithm is described to assign test cubes to polynomials in a way that enhances encoding efficiency. For hardware security, a new attack strategy against logic obfuscation is described here. It is based on applying brute force iteratively to each logic cone one at a time and is shown to significantly reduce the number of brute force key combinations that need to be tried by an attacker. It is shown that inserting key gates based on MUXes is an effective approach to increase security against this type of attack. In data security for hardware, existing techniques for computing with encrypted operands are either prohibitively expense (e.g., fully homomorphic encryption) or only work for special cases (e.g., linear circuits). A lightweight scheme implemented at the gate-level is proposed for computing with noise-obfuscated data. By carefully selecting internal locations for noise cancellation in arbitrary logic circuits, the overhead can be greatly minimized. One important application of the proposed scheme is for protecting data inside a computing unit obtained from a third party IP provider where a hidden backdoor access mechanism or hardware Trojan could be maliciously inserted.
dc.description.departmentElectrical and Computer Engineering
dc.format.mimetypeapplication/pdf
dc.identifier.urihttps://hdl.handle.net/2152/75347
dc.identifier.urihttp://dx.doi.org/10.26153/tsw/2452
dc.language.isoen
dc.subjectDFT
dc.subjectSecure computing
dc.subjectTest compression
dc.subjectData obfuscation
dc.subjectLogic obfuscation
dc.titleTest and security in a System-on-Chip environment
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorThe University of Texas at Austin
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy

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