Improved architectures for fused floating-point arithmetic units
| dc.contributor.advisor | Swartzlander, Earl E., Jr., 1945- | |
| dc.creator | Sohn, Jongwook | en |
| dc.date.accessioned | 2013-11-05T18:29:13Z | en |
| dc.date.issued | 2013-05 | en |
| dc.date.submitted | May 2013 | en |
| dc.date.updated | 2013-11-05T18:29:14Z | en |
| dc.description | text | en |
| dc.description.abstract | Most general purpose processors (GPP) and application specific processors (ASP) use the floating-point arithmetic due to its wide and precise number system. However, the floating-point operations require complex processes such as alignment, normalization and rounding. To reduce the overhead, fused floating-point arithmetic units are introduced. In this dissertation, improved architectures for three fused floating-point arithmetic units are proposed: 1) Fused floating-point add-subtract unit, 2) Fused floating-point two-term dot product unit, and 3) Fused floating-point three-term adder. Also, the three fused floating-point units are implemented for both single and double precision and evaluated in terms of the area, power consumption, latency and throughput. To improve the performance of the fused floating-point add-subtract unit, a new alignment scheme, fast rounding, two dual-path algorithms and pipelining are applied. The improved fused floating-point two-term dot product unit applies several optimizations: a new alignment scheme, early normalization and fast rounding, four-input leading zero anticipation (LZA), dual-path algorithm and pipelining. The proposed fused floating-point three-term adder applies a new exponent compare and significand alignment scheme, double reduction, early normalization and fast rounding, three-input LZA and pipelining to improve the performance. | en |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/2152/21943 | en |
| dc.language.iso | en_US | en |
| dc.subject | Floating-point arithmetic | en |
| dc.subject | Fused floating-point operation | en |
| dc.subject | High speed computer arithmetic | en |
| dc.subject | Add-subtract unit | en |
| dc.subject | Dot product unit | en |
| dc.subject | Three-term adder | en |
| dc.title | Improved architectures for fused floating-point arithmetic units | en |
| thesis.degree.department | Electrical and Computer Engineering | en |
| thesis.degree.discipline | Electrical and Computer Engineering | en |
| thesis.degree.grantor | The University of Texas at Austin | en |
| thesis.degree.level | Doctoral | en |
| thesis.degree.name | Doctor of Philosophy | en |