Incorporating the effect of delay variability in path based delay testing
| dc.contributor.advisor | Abraham, Jacob A. | en |
| dc.creator | Tayade, Rajeshwary G. | en |
| dc.date.accessioned | 2009-10-19T17:00:12Z | en |
| dc.date.available | 2009-10-19T17:00:12Z | en |
| dc.date.issued | 2009-05 | en |
| dc.description | text | en |
| dc.description.abstract | Delay variability poses a formidable challenge in both design and test of nanometer circuits. While process parameter variability is increasing with technology scaling, as circuits are becoming more complex, the dynamic or vector dependent variability is also increasing steadily. In this research, we develop solutions to incorporate the effect of delay variability in delay testing. We focus on two different applications of delay testing. In the first case, delay testing is used for testing the timing performance of a circuit using path based fault models. We show that if dynamic delay variability is not accounted for during the path selection phase, then it can result in targeting a wrong set of paths for test. We have developed efficient techniques to model the effect of two different dynamic effects namely multiple-input switching noise and coupling noise. The basic strategy to incorporate the effect of dynamic delay variability is to estimate the maximum vector delay of a path without being too pessimistic. In the second case, the objective was to increase the defect coverage of reliability defects in the presence of process variations. Such defects cause very small delay changes and hence can easily escape regular tests. We develop a circuit that facilitates accurate control over the capture edge and thus enable faster than at-speed testing. We further develop an efficient path selection algorithm that can select a path that detects the smallest detectable defect at any node in the presence of process variations. | en |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.medium | electronic | en |
| dc.identifier.uri | http://hdl.handle.net/2152/6559 | en |
| dc.language.iso | eng | en |
| dc.rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. | en |
| dc.subject | Delay testing | en |
| dc.subject | Delay variability | en |
| dc.subject | Path based delay testing | en |
| dc.subject | Path selection | en |
| dc.subject | Path selection algorithms | en |
| dc.subject | Delay fault models | en |
| dc.subject | Multiple-input switching | en |
| dc.subject | Coupling noise | en |
| dc.subject | Nanometer circuits | en |
| dc.title | Incorporating the effect of delay variability in path based delay testing | en |
| thesis.degree.department | Electrical and Computer Engineering | en |
| thesis.degree.discipline | Electrical and Computer Engineering | en |
| thesis.degree.grantor | The University of Texas at Austin | en |
| thesis.degree.level | Doctoral | en |
| thesis.degree.name | Doctor of Philosophy | en |