Eksen : regression test selection for VHDL

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dc.contributor.advisorKhurshid, Sarfraz
dc.contributor.committeeMemberGligoric, Milos
dc.creatorLoyola, Jose Luis
dc.date.accessioned2018-02-26T17:48:30Z
dc.date.available2018-02-26T17:48:30Z
dc.date.created2017-12
dc.date.issued2018-01-26
dc.date.submittedDecember 2017
dc.date.updated2018-02-26T17:48:30Z
dc.description.abstractRegression testing - running tests after a change - has become a critical component of software development, but as projects grow bigger it becomes a time consuming task. For this reason Regression Test Selection (RTS) techniques have become very important. RTS consists of analyzing the changes to a code base and selecting a subset of tests to be run based on these changes. In the context of regression testing, VHDL development is not so different from any other programming language. Modules have unit tests and integration tests. Similarly, the larger the project, the longer it takes to run the test suite. We propose Eksen, a tool for VHDL test selection inspired by the Ekstazi tool for Java. Eksen keeps track of which files have changed including its dependencies and uses this information to select which tests must be run. Eksen statically analyzes the VHDL file dependency tree, it determines which files are affected by the change and only run the tests from that dependency branch. By targeting only the tests on the dependency branch, Eksen can significantly reduce the test suite execution time. For evaluation purposes, we implemented two versions of Eksen: one using VUnit (an open-source VHDL testing framework). The second using a proprietary enterprise VHDL compiler. This allowed us to verify the time savings on a real industrial projects. Eksen was able to cut test time in half on some of these projects. The results of this experiment are presented in the evaluation section.
dc.description.departmentElectrical and Computer Engineering
dc.format.mimetypeapplication/pdf
dc.identifierdoi:10.15781/T2ZK56386
dc.identifier.urihttp://hdl.handle.net/2152/63753
dc.language.isoen
dc.subjectRegression
dc.subjectTest
dc.subjectSelection
dc.subjectVHDL
dc.subjectRTS
dc.titleEksen : regression test selection for VHDL
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorThe University of Texas at Austin
thesis.degree.levelMasters
thesis.degree.nameMaster of Science in Engineering

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