Nanostructuring approaches to altering and enhancing performance characteristics of thin-film transistors

Nanostructured thin-film transistor (TFT) designs and approaches in this work have been shown to enhance transistor characteristics across many semiconductor materials. We highlight two nanostructuring approaches, including nanostripe patterning of the transistor channel and nanospike patterning of the source and drain electrodes. Both nanostructuring techniques are shown to alter and improve transistor performance by (i) enhancing gate control which improves subthreshold characteristics, (ii) enhancing electric fields and carrier concentrations near the source contact to improve carrier injection, and (iii) redistributing the carrier concentrations within the channel resulting in enhanced concentrations in narrow channels designated as charge nanoribbons. Nanostripe-patterning of semiconductor channels was studied with technology computer-assisted design (TCAD) software and shown to enhance transistor drive currents over unpatterned channels by greater than a factor of 11 and showed that the nanostripe patterning of the semiconductor channel resulted in reduced short channel effects and significantly improved gate control. The advantages of nanostripe channel patterning were also demonstrated experimentally and showed enhancement of carrier mobility by a factor of 2. Nanospike-patterning of the metal source and drain electrode TFTs were also explored and shown, through experimental studies and simulation studies, to substantially improve the performance of TFTs, especially at short channel lengths and also below threshold. Inspired by field emission contacts and our nanostripe work, the sharp tip of the nanospike electrodes focus electric fields and produces field-emission enhanced carrier injection from the nanospike source and drain contacts, leading to higher drive currents, carrier densities, and carrier velocities. Nanospike electrodes also facilitate quasi-three-dimensional gate control, especially at low gate voltage conditions. This leads to significantly improved subthreshold characteristics and reduced subthreshold dependence on drain voltage, especially at short channel lengths. While nanospike electrode TFTs do not have physically patterned semiconductor regions as nanostripe TFTs, nanospike electrode TFTs also form charge nanoribbons at high drain voltages which similarly facilitates superior gate control over the full channel. Both nanostripe semiconductor TFTs and nanospike electrode TFTs are promising approaches that are compatible with many thin-film semiconductor materials, fabrication methods, and design strategies. These nanostructuring strategies can improve processing speed and performance while reducing power consumption when applied to flexible electronic systems or in back-end-of-the-line circuits.