Browsing by Subject "Interconnect"
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Item 3D system-circuit-device design methodologies for advanced CMOS(2021-05-03) Mathur, Rahul; Kulkarni, Jaydeep P.; John, Lizy; Dodabalapur, Ananth; Banerjee, Sanjay; Yeric, Greg; Sinha, SaurabhThe emergence of 5G, automotive, and AI-based applications are creating new capabilities and a huge amount of data that is driving the need for a broad expansion in energy-efficient compute capacities. At the same time, the typical gains in Power, Performance, Area, and Cost (PPAC) that dimensional scaling has brought over the past several decades are slowing down. To o set the slowdown in 2D scaling and continue the trajectory of PPAC improvements, coordinated innovations are needed across the system, circuit, and device abstraction levels. 3D integration may offer complementary gains to transistor density scaling. Meanwhile, 3D expands the design space of SoC adding considerations like partitioning, power delivery, signaling, and thermal management. This dissertation studies these considerations in detail. The work spans thermal analysis of a 3D CPU, system-level design space exploration of 3D ML accelerators, circuit design of a 3D-Split SRAM macro, and novel use of device-level 3D construct of Buried Power Rail (BPR) for SRAM signaling to enable next-generation computing systems in advanced CMOS.Item Analysis of high performance interconnect in SoC with distributed switches and multiple issue bus protocols(2011-05) Narayanasetty, Bhargavi; John, Lizy Kurian; Korson, SteveIn a System on a Chip (SoC), interconnect is the factor limiting Performance, Power, Area and Schedule (PPAS). Distributed crossbar switches also called as Switching Central Resources (SCR) are often used to implement high performance interconnect in a SoC – Network on a Chip (NoC). Multiple issue bus protocols like AXI (from ARM), VBUSM (from TI) are used in paths critical to the performance of the whole chip. Experimental analysis of effects on PPAS by architectural modifications to the SCRs is carried out, using synthesis tools and Texas Instruments (TI) in house power estimation tools. The effects of scaling of SCR sizes are discussed in this report. These results provide a quick means of estimation for architectural changes in the early design phase. Apart from SCR design, the other major domain, which is a concern, is deadlocks. Deadlocks are situations where the network resources are suspended waiting for each other. In this report various kinds of deadlocks are classified and their respective mitigations in such networks are provided. These analyses are necessary to qualify distributed SCR interconnect, which uses multiple issue protocols, across all scenarios of transactions. The entire analysis in this report is carried out using a flagship product of Texas Instruments. This ASIC SoC is a complex wireless base station developed in 2010- 2011, having 20 major cores. Since the parameters of crossbar switches with multiple issue bus protocols are commonly used in SoCs across the semiconductor industry, this reports provides us a strong basis for architectural/design selection and validation of all such high performance device interconnects. This report can be used as a seed for the development of an interface tool for architects. For a given architecture, the tool suggests architectural modifications, and reports deadlock situations. This new tool will aid architects to close design problems and bring provide a competitive specification very early in the design cycle. A working algorithm for the tool development is included in this report.Item Application of digital calibration technique on global bidirectional interconnects in integrated circuit(2014-12) Saetow, Anuwat; Pan, David Z.The trend to integrate more and more processing cores and memory cores into a single module has increased the overall size of chips to the point where global interconnects between sub-units are becoming harder and harder to route and meet timing rules and requirements. The traditional way of routing interconnects and the use of uniform, unidirectional, point to point busses may no longer be optimal for certain designs where metal layers and chip area for interconnects are limited. The need for a more flexible routing methodology is necessary and can be achieved by using routing and calibration techniques currently being implemented at board level design. This report proposes the use of non-uniform, bidirectional, and possibly multi-point loads global interconnects within a single chip module through the use of on chip calibration techniques to compensate for less restrictive wiring rules for certain chip designs. This report will also apply a widely used digital calibration technique to simulate the implementation on a field programmable gate array.