3D system-circuit-device design methodologies for advanced CMOS

The emergence of 5G, automotive, and AI-based applications are creating new capabilities and a huge amount of data that is driving the need for a broad expansion in energy-efficient compute capacities. At the same time, the typical gains in Power, Performance, Area, and Cost (PPAC) that dimensional scaling has brought over the past several decades are slowing down. To o set the slowdown in 2D scaling and continue the trajectory of PPAC improvements, coordinated innovations are needed across the system, circuit, and device abstraction levels. 3D integration may offer complementary gains to transistor density scaling. Meanwhile, 3D expands the design space of SoC adding considerations like partitioning, power delivery, signaling, and thermal management. This dissertation studies these considerations in detail. The work spans thermal analysis of a 3D CPU, system-level design space exploration of 3D ML accelerators, circuit design of a 3D-Split SRAM macro, and novel use of device-level 3D construct of Buried Power Rail (BPR) for SRAM signaling to enable next-generation computing systems in advanced CMOS.