Browsing by Subject "Germanium compounds"
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Item Fabrication modeling and reliability of novel architecture and novel materials based MOSFET devices(2006) Dey, Sagnik; Banerjee, SanjayAs device dimensions are scaled beyond the 45nm node, new device architectures and new materials need to be examined which are able to address the technological challenges and meet the requirements for sub-50nm MOSFETs. In this dissertation an alternate MOSFET device architecture is proposed that is not only capable of excellent subthreshold characteristics and off-state leakage current but also enhanced drive currents leading to high ION/IOFF ratio that can make it a suitable candidate for replacing the planar MOSFET as scaling is extended beyond the 45nm CMOS technology node. The proposed MOSFET device is formed by a fully-depleted Si cantilever channel suspended between source/drain “anchors” wrapped all-around by the gate. The device architecture proposed is further integrated with a high-k dielectric and metal gate, making it more amenable to scaling. In addition to novel architectures, high mobility novel material based channel engineering has also emerged as an attractive alternative for performance enhancements beyond sub-50nm nodes. If such materials such as Ge, or SiGe or strained-Si are to be used in production they need to be integrated on Si substrates from the cost and manufacturability point of view, along with concomitant requirements of good material quality and simple processing. This dissertation describes a technique of epitaxially growing high quality pure Ge-on-bulk Si substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD). The Ge layer is grown on thin SiGe layers with rapidly-varying Ge mole fraction which have been shown to block misfit dislocation defects. A similar technique to implement biaxially-tensile-strained Si on ultra-thin dislocation blocking buffer layers is also demonstrated. NMOSFETs fabricated on the strained-Si channels showed significant enhancements in mobility. This dissertation also demonstrates integration of high-mobility SiGe with the fully-depleted gate-all-around cantilever channel architecture which might be suitable for high performance devices. Finally modeling and analysis of hot carrier reliability of strained Si devices is included for Intel’s 65nm and 90nm nodes, along with studies of low frequency noise degradation.Item Gate dielectrics on strained SiGe(2002-12) Ngai, Tat; Banerjee, SanjayBuried channel SiGe PMOSFET performance is degraded by the requirement of Si caps. However, fabrication of surface channel SiGe PMOSFETs has rarely been successful due to gate oxide problems. Low temperature deposited SiO2 using remote plasma CVD (RPCVD) and high-k gate dielectric ZrO2 using DC magnetron reactive sputtering have been investigated for SiGe applications in this work. A low temperature gate quality silicon dioxide process has been developed using Remote Plasma Chemical Vapor Deposition (RPCVD). By carefully controlling the background water concentration, a high quality SiO2/Si interface can be achieved even without the pre-oxidation. RPCVD oxide films deposited on Si have excellent as-deposited interfacial (Dit ~ 1x1010 cm -2eV-1) and bulk (Ebd > 10 MV/ cm) electrical properties. However, SiGe MOSFETs with high quality RPCVD SiO2 still under-perform Si devices because of a poor interface. Low temperature water vapor annealing seems to be very effective to passivate the dangling bonds at the SiO2/SiGe interface. More than 20% transconductance improvement is observed in SiGe devices after water vapor annealing. This dissertation also reports the electrical properties of a high-k material, ZrO2, deposited directly on SiGe, without the use of a Si cap layer or a passivation barrier. ZrO2 thin films of equivalent oxide thickness (EOT) down to 16.5 Å were deposited on strained SiGe layers by reactive sputtering. Results indicate that ZrO2 films on SiGe have good interfacial properties and low leakage currents. Silicon and surface channel SiGe PMOSFETs using a ZrO2 gate dielectric with EOT less than 20 Å was fabricated. Mobility enhancement is also observed in SiGe devices. ZrO2 shows great promise as an alternative gate dielectric for SiGe applications.Item Investigation of use of ALE techniques for fabrication of novel structures in Si and Ge(1995-08) Mahajan, Avinash Prabhakar, 1968-; Not availableItem Metal-oxide-semiconductor devices based on epitaxial germanium layers grown selectively directly on silicon substrates by ultra-high-vacuum chemical vapor deposition(2009-05) Donnelly, Joseph Patrick, 1965-; Banerjee, SanjayThis document details experiments attempting to increase the performance of metal-oxide-semiconductor field-effect-transistors (MOSFETs) which are the mainstay of the semiconductor industry. Replacing the silicon channel with an ultra-thin epitaxial germanium layer grown selectively on a silicon (100) bulk wafer is examined in detail. The gate oxide chosen for the germanium devices is a high-k gate oxide, HfO2, and the gate electrode is a metal gate, tantalum-nitride. They demonstrate large improvements in drive current and mobility over identically processed silicon PMOSFETs. In addition to the planar germanium PMOSFETs, a process has been developed for 50nm and smaller germanium P-finFETs and N and P germanium tunnel-FETs. The patterning of sub-30nm wide and 230nm tall three dimensional fins has been done with electron beam lithography and dry plasma etching. The processes to deposit high-k gate oxide and metal gates on the sub-30nm wide fins have been developed. All that remains for the production of these devices is electron beam lithography with a maximum misalignment error of 40nm.Item Metal-oxide-semiconductor devices based on epitaxial germanium-carbon layers grown directly on silicon substrates by ultra-high-vacuum chemical vapor deposition(2006) Kelly, David Quest; Banerjee, SanjayAfter the integrated circuit was invented in 1959, complementary metal-oxidesemiconductor (CMOS) technology soon became the mainstay of the semiconductor industry. Silicon-based CMOS has dominated logic technologies for decades. During this time, chip performance has grown at an exponential rate at the cost of higher power consumption and increased process complexity. The performance gains have been made possible through scaling down circuit dimensions by improvements in lithography capabilities. Since scaling cannot continue forever, researchers have vigorously pursued new ways of improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) without having to shrink gate lengths and reduce the gate insulator thickness. Strained silicon, with its ability to boost transistor current by improving the channel mobility, is one of the methods that has already found its way into production. viii Although not yet in production, high-κ dielectrics have also drawn wide interest in industry since they allow for the reduction of the electrical oxide thickness of the gate stack without having to reduce the physical thickness of the dielectric. Further out on the horizon is the incorporation of high-mobility materials such as germanium (Ge), silicongermanium (Si1-xGex), and the III-V semiconductors. Among the high-mobility materials, Ge has drawn the most attention because it has been shown to be compatible with high-κ dielectrics and to produce high drive currents compared to Si. Among the most difficult challenges for integrating Ge on Si is finding a suitable method for reducing the number of crystal defects. The use of strainrelaxed Si1-xGex buffers has proven successful for reducing the threading dislocation density in Ge epitaxial layers, but questions remain as to the viability of this method in terms of cost and process complexity. This dissertation presents research on thin germanium-carbon (Ge1-yCy) layers on Si for the fabrication of MOS transistors with improved drive currents. By incorporating a small amount of C in Ge, the crystal quality of Ge epitaxial layers grown directly on Si can be dramatically improved. The Ge1-yCy layers have been used to fabricate high-drivecurrent p-MOSFETs with high-κ dielectrics and metal gates. In addition to the electrical results, materials-related experimental data was acquired and analyzed to provide insights on the surface morphology, crystal quality, strain, C incorporation, and growth kinetics of the Ge1-yCy layers. This work describes an exciting new possibility for the ultimate goal of incorporating high-mobility semiconductor materials in CMOS technology.