Fabrication modeling and reliability of novel architecture and novel materials based MOSFET devices

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Dey, Sagnik

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As device dimensions are scaled beyond the 45nm node, new device architectures and new materials need to be examined which are able to address the technological challenges and meet the requirements for sub-50nm MOSFETs. In this dissertation an alternate MOSFET device architecture is proposed that is not only capable of excellent subthreshold characteristics and off-state leakage current but also enhanced drive currents leading to high ION/IOFF ratio that can make it a suitable candidate for replacing the planar MOSFET as scaling is extended beyond the 45nm CMOS technology node. The proposed MOSFET device is formed by a fully-depleted Si cantilever channel suspended between source/drain “anchors” wrapped all-around by the gate. The device architecture proposed is further integrated with a high-k dielectric and metal gate, making it more amenable to scaling. In addition to novel architectures, high mobility novel material based channel engineering has also emerged as an attractive alternative for performance enhancements beyond sub-50nm nodes. If such materials such as Ge, or SiGe or strained-Si are to be used in production they need to be integrated on Si substrates from the cost and manufacturability point of view, along with concomitant requirements of good material quality and simple processing. This dissertation describes a technique of epitaxially growing high quality pure Ge-on-bulk Si substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD). The Ge layer is grown on thin SiGe layers with rapidly-varying Ge mole fraction which have been shown to block misfit dislocation defects. A similar technique to implement biaxially-tensile-strained Si on ultra-thin dislocation blocking buffer layers is also demonstrated. NMOSFETs fabricated on the strained-Si channels showed significant enhancements in mobility. This dissertation also demonstrates integration of high-mobility SiGe with the fully-depleted gate-all-around cantilever channel architecture which might be suitable for high performance devices. Finally modeling and analysis of hot carrier reliability of strained Si devices is included for Intel’s 65nm and 90nm nodes, along with studies of low frequency noise degradation.