Browsing by Subject "Electronic circuit design--Economic aspects"
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Item Cost-effective test at system-level(2002-12) Kim, Hyun-moo, 1970-; Ambler, TonyAs modern digital hardware/software systems become more complex, the testing of these systems through their entire life-cycle including design verification test, production test, and field test, becomes a severe problem. In addition, the system's own characteristics make it difficult to apply componentlevel test methods for system-level testing. The goal of this dissertation is to provide help in obtaining a cost-effective test model that can be used at systemlevel and with testability at field-level. Equation-based method can be used in finding an appropriate test method, but to use this method, all the cost-related equations have to be developed, which is a very difficult and time-consuming process. At the initial design stage, some parameters are not available, and many are not accurate. A new test selection method using multi-attribute utility analysis (MAUA) is suggested in this dissertation. This method can greatly reduce time in developing model. This dissertation applies MAUA method to chip-level test selection to determine its usefulness, and goes on to apply it to system-level test selection. The results show that the applications of this method in the test selection of chip-level and single-board computer (SBC) point towards the best test method with much less effort compared to when traditional cost equations are developed.Item Reducing power consumption during online and offline testing(2005) Ghosh, Shalini; Touba, Nur A.This dissertation proposes techniques for power reduction in online and offline circuit testing. Power management is critical in both these domains, since high power dissipation can drive up production cost and even cause errors. The first part of the dissertation focuses on power reduction for online testing with concurrent error detection capabilities, where errors in the operation of the circuit are detected (and possibly corrected) at normal operational run-time. In online testing, power dissipation has lately become a first-order design criterion due to the significant hardware overhead for detecting/correcting errors and ensuring system reliability. Two problems are addressed, namely reducing power in concurrent error detection for (1) error correcting codes for memory checker, and (2) synthesis of parity prediction circuits. The next part of the dissertation discusses power reduction for offline testing. With the advent of high-performance and low-power devices, the power consumed during circuit testing has become a critical issue since the power dissipated in a circuit during the testing phase can be much larger than the power consumed during normal operation. Techniques are presented for reducing power in two popular methods of offline circuit testing: (1) scan testing, and (2) built-in self-test.