Reducing power consumption during online and offline testing

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Date

2005

Authors

Ghosh, Shalini

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Abstract

This dissertation proposes techniques for power reduction in online and offline circuit testing. Power management is critical in both these domains, since high power dissipation can drive up production cost and even cause errors. The first part of the dissertation focuses on power reduction for online testing with concurrent error detection capabilities, where errors in the operation of the circuit are detected (and possibly corrected) at normal operational run-time. In online testing, power dissipation has lately become a first-order design criterion due to the significant hardware overhead for detecting/correcting errors and ensuring system reliability. Two problems are addressed, namely reducing power in concurrent error detection for (1) error correcting codes for memory checker, and (2) synthesis of parity prediction circuits. The next part of the dissertation discusses power reduction for offline testing. With the advent of high-performance and low-power devices, the power consumed during circuit testing has become a critical issue since the power dissipated in a circuit during the testing phase can be much larger than the power consumed during normal operation. Techniques are presented for reducing power in two popular methods of offline circuit testing: (1) scan testing, and (2) built-in self-test.

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