Browsing by Subject "Dynamic amplifier"
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Item Design of high-linearity PVT-robust dynamic amplifier(2019-05-08) Zhang, Mantian; Sun, NanModern electronic device market demands high power-efficiency, high-speed, and high-resolution analog-to-digital converters (ADC). Amplifiers be-come increasingly significant in the high-performance ADC design. Dynamic amplifier stands out for its low power consumption feature. However, the process-voltage-temperature (PVT) variation and limited linearity prevent it from wide usage. This thesis presents a high-linearity and PVT-robust dynamic amplifier. It implements the capacitively degenerated linearization (CDL) method to achieve high linearity. Furthermore, it combines a PVT-sensing amplifier and a voltage-to-time (V2T) converter as the control timer. Once the foreground calibration is done, the proposed dynamic amplifier will track the PVT variation and provide high-linearity and stable gain. Compared to the conventional CDL dynamic amplifier and the PVT-stabilized dynamic amplifier, this design suffers from less gain variation over PVT fluctuation while exhibiting high linearity. Therefore, it suits the application of the pipeline ADC and other types of ADC. A design prototype in schematic level is implemented in 40nm TSMC CMOS technology. The simulation results indicate that the circuit provides less than −80dB total-harmonics-distortion (THD), ranging from−15°C to 100°C with 140mV peak-to-peak differential sinusoidal input. When the supply voltage varies from 1.15V to 1.25V, the gain variation of this design is within ±2.5% and the THD is less than −75dB.Item High-performance oversampling A/D converter design techniques in scaled CMOS technologies(2018-05-03) Li, Shaolan; Sun, Nan; Pan, David; Orshansky, Micheal; Viswanathan, T. R.; Soenen, EricOversampling analog-to-digital converters (ADCs) are specialists in digitizing real-word signals in high resolution. They have been crucial building blocks in many modern electronic systems, and are expected to have a growing significance in the booming era of Internet-of-Things (IoT). However, many classic oversample ADC techniques are power-hungry and scaling-unfriendly, making them deficient for many emerging applications. To address this challenge, this thesis explores solution from two directions: voltage-controlled-oscillator (VCO)-based ADC and hybrid ADC. The first work presents a VCO-based ADC featuring a novel phase- extended-quantizer (PEQ). Compared to prior VCO-based ADCs, the proposed phase extension technique enabled this work to achieve 1-bit higher resolution with very little power and circuit overhead. On top of resolution boosting, A tri-level resistor digital-to-analog converter (DAC) is also introduced as complementary to the new quantizer, enabling high DR while creating a dynamic power saving mechanism for the proposed design. Fabricated in 130 nm CMOS, the prototype ADC achieved peak Schreier Figure-of-Merits (FoM) of 174.3 dB, marking 2.5x improvement over prior arts. The second project extends the achievement of the first and develops techniques to push the performance frontier of high-order VCO-based ADC. Existing high-order VCO-based ADCs still rely on OTA-based active loop filter, which deemphasizes the merits of the VCO-based quantizer. To address their limitation, a hybrid "passive + VCO" architecture is proposed, where we made the front-end loop filter fully passive and zero-power, and used the VCO to support the entire loop gain. This technique innovatively utilizes the parasitic effect of the VCO, hence also obviates the need for parasitic cancellation. A prototype fabricated in 40 nm CMOS measured 19 fJ/conversion Walden FoM, achieving 5x improvement over existing high-order VCO-based ADC. Finally, this thesis also presents the design of a noise-shaping SAR (NS-SAR) ADC. Unlike prior works that all rely on the cascaded integrator feed-forward (CIFF) structure, this work distinctively employs the error-feedback (EF) structure. It is the first in its kind to achieves second-order NTF with complex zero optimization, using all low-power scaling-friendly building blocks such as passive finite-impulse-response (FIR) filter and dynamic amplifier (D-Amp). A background calibration scheme is also developed to improve robustness over process-voltage-temperature (PVT) variation. The prototype chip fabricated in 40nm CMOS measured the state-of-the-art performance of 178 dB Schreier FoM. This works demonstrated a NS-SAR solution that combines optimized NTF, power efficiency and PVT robustnessItem Utilizing digital design techniques and circuits to improve energy and design efficiency of analog and mixed-signal circuits(2021-05-01) Gandara, Miguel Francisco; Pan, David Z.; Sun, Nan; Soenen, Eric; Gharpurey, Ranjit; Orshansky, Michael ETechnology scaling has long driven large growth in the electronics market. With each successive technology generation, digital circuits become more power and area efficient. The large performance increases realized for digital circuits due to digital scaling have not translated to similar performance improvements for analog circuits. First, noise-limited analog circuits are not capable of leveraging the reduced parasitics of advanced processes, since capacitor sizes are generally set by noise requirements. Second, analog circuit performance is closely tied to the achievable device intrinsic gain, which degrades as process sizes shrink. Reduced supply voltages further exacerbate this issue, as the achievable gain per stage is limited by the number of devices that can be stacked while maintaining all devices in saturation. Finally, process variation increases with decreased feature sizes, so analog circuits have deal with increased mismatch and wider variations in threshold voltages, increasing the time required to design a circuit that is robust across process, voltage, and temperature (PVT) variation. This work seeks to address the limitations of analog circuits in advanced technologies by leveraging digital techniques and digital-like circuits that offer improved scalability. The first half of this dissertation investigates replacing the traditional closed-loop residue amplifier in a pipeline analog-to-digital converter (ADC) with an open loop dynamic amplifier. Previous works incorporating dynamic amplifiers have struggled to achieve large gains and have suffered from offset mismatch between the comparator and amplifier, which will only get worse in more advanced technologies. We propose the usage of a residue amplifier that combines an integration stage, to ensure low noise operation, with a positive feedback stage, to ensure high gain and high speed operation. By utilizing this topology, the proposed amplifier was the first dynamic amplifier to achieve a high gain of 32. Additionally, the proposed amplifier can reuse existing comparator hardware in the ADC, removing all offset mismatch between comparator and amplifier. Digital calibration techniques were applied to ensure a constant gain across PVT. The next part of this dissertation tries to overcome the scaling challenges for noise-limited ADCs with band-limited input signals. By leveraging digital filtering techniques to generate a prediction of the band-limited signal, the conversion can be limited to a range that is a fraction of the total ADC input range, allowing for significant decreases in reference and comparator power consumption. This work extends previous works by enabling accurate predictions for any band-limited signal characteristic. Previous works only focused on accurate predictions for low-activity signals. Finally, the large compute power enabled by modern technology scaling is leveraged to improve the design efficiency of analog circuits. A new automated circuit sizing tool is proposed that can achieve better performance than manual designs done by experts in a much shorter amount of time. All of these techniques help to alleviate the power and design efficiency limitations caused by technology scaling.