Design of high-linearity PVT-robust dynamic amplifier

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Date

2019-05-08

Authors

Zhang, Mantian

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Abstract

Modern electronic device market demands high power-efficiency, high-speed, and high-resolution analog-to-digital converters (ADC). Amplifiers be-come increasingly significant in the high-performance ADC design. Dynamic amplifier stands out for its low power consumption feature. However, the process-voltage-temperature (PVT) variation and limited linearity prevent it from wide usage. This thesis presents a high-linearity and PVT-robust dynamic amplifier. It implements the capacitively degenerated linearization (CDL) method to achieve high linearity. Furthermore, it combines a PVT-sensing amplifier and a voltage-to-time (V2T) converter as the control timer. Once the foreground calibration is done, the proposed dynamic amplifier will track the PVT variation and provide high-linearity and stable gain. Compared to the conventional CDL dynamic amplifier and the PVT-stabilized dynamic amplifier, this design suffers from less gain variation over PVT fluctuation while exhibiting high linearity. Therefore, it suits the application of the pipeline ADC and other types of ADC. A design prototype in schematic level is implemented in 40nm TSMC CMOS technology. The simulation results indicate that the circuit provides less than −80dB total-harmonics-distortion (THD), ranging from−15°C to 100°C with 140mV peak-to-peak differential sinusoidal input. When the supply voltage varies from 1.15V to 1.25V, the gain variation of this design is within ±2.5% and the THD is less than −75dB.

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