Si/Ge heterojunction tunnel FETs for low power applications and junction engineering in germanium MOSFETs for high performance applications

dc.contributor.advisorBanerjee, Sanjay
dc.contributor.committeeMemberTutuc, Emanuel
dc.contributor.committeeMemberRegister, Leonard F.
dc.contributor.committeeMemberLee, Jack C.
dc.contributor.committeeMemberBonnecaze, Roger T.
dc.creatorHsu, William, Ph. D.
dc.creator.orcid0000-0002-3491-544X 2016
dc.description.abstractPower dissipation has become one of the most significant impediments to continued scaling of complementary metal-oxide-semiconductor (CMOS) technology. Two approaches have been proposed for enabling supply power scaling: (i) reduction of subthreshold swing (SS) with novel operation mechanisms, and (ii) increasing of ON-current with high mobility materials or advanced device architectures. In this work, two alternative devices, tunnel field-effect transistors (TFETs) and Ge-channel MOSFETs, are being explored as possible solutions to these two approaches, respectively. TFETs have the potential to achieve a SS steeper than the thermionic emission defined limit of 60 mV/dec at room temperature to which MOSFETs are subject and, thus, enable lower voltage, lower power logic. On the other hand, Ge is promising as the enabler for high mobility channel, offering the potential to further enhance ON-current. The compatibility with conventional Si CMOS manufacturing makes Ge very attractive compared to other high mobility materials (e.g. III-V). In the first part, a Si-technology compatible Si/Ge heterojunction TFET is proposed. The device design utilizes a strained-Si/strained-Ge vertical heterojunction to provide a staggered-gap band alignment with small effective band gap and gate normal tunneling. Performance evaluation by simulation suggests that the device has the potential to be competitive with modern MOSFETs. In addition, device design guidelines in terms of electrostatic control are discussed while considering the quantum effects. In the second part, we focus on source/drain junction engineering for Ge CMOS. For n-type junctions, advanced activation scheme using non-melt sub-millisecond laser spike annealing is utilized to demonstrate excellent diffusion control and high activation level. For p-type junctions, novel BF implantation is shown to offer a higher B activation level and a shallower junction depth in Ge as compared to B and BF2 implantations. The detail diffusion mechanism of B in the presence of F is studied. High performance Ge n-type and p-type diodes are obtained along with significant reduction of contact resistance, and integration in a MOSFET process flow.
dc.description.departmentElectrical and Computer Engineering
dc.subjectTunnel field-effect transistor
dc.subjectSi/Ge heterojunction
dc.subjectGate-normal tunneling
dc.subject2D-2D tunneling
dc.subjectDopant activation
dc.subjectDopant deactivation
dc.subjectLaser spike annealing
dc.subjectPn junction
dc.subjectShallow junction
dc.subjectSheet resistance
dc.subjectContact resistivity
dc.subjectJunction leakage
dc.subjectGate-induced drain leakage
dc.titleSi/Ge heterojunction tunnel FETs for low power applications and junction engineering in germanium MOSFETs for high performance applications
dc.type.materialtext and Computer Engineering and Computer engineering University of Texas at Austin of Philosophy

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