Analog-to-digital converter circuit and system design to improve with CMOS scaling
| dc.contributor.advisor | Evans, Brian L. (Brian Lawrence), 1965- | en |
| dc.contributor.advisor | Hassibi, Arjang | en |
| dc.contributor.committeeMember | Humphreys, Todd E | en |
| dc.contributor.committeeMember | Swartlzander, Earl E | en |
| dc.contributor.committeeMember | Tewfik, Ahmed H | en |
| dc.creator | Mortazavi, Yousof | en |
| dc.creator.orcid | 0000-0001-9037-4740 | en |
| dc.date.accessioned | 2015-09-08T19:28:40Z | en |
| dc.date.issued | 2015-05 | en |
| dc.date.submitted | May 2015 | en |
| dc.date.updated | 2015-09-08T19:28:40Z | en |
| dc.description | text | en |
| dc.description.abstract | There is a need to rethink the design of analog/mixed-signal circuits to be viable in state-of-the-art nanometer-scale CMOS processes due to the hostile environment they create for analog circuits. Reduced supply voltages and smaller capacitances are beneficial to circuit speed and digital circuit power efficiency; however, these changes along with smaller dimensions and close coupling of fast-switching digital circuits have made high-accuracy voltage domain analog processing increasingly difficult. In this work, techniques to improve analog-to-digital converters (ADC) for nanometer-scale processes are explored. First, I propose a mostly-digital time-based oversampling delta-sigma (∆Σ) ADC architecture. This system uses time, rather than voltage, as the analog variable for its quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital "pulse." The merits of this architecture render it not only viable to scaling, but also enable improved circuit performance with ever-increasing time resolution of scaled CMOS processes. This is in contrast to traditional voltage-based analog circuit design, whose performance generally decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage reduction and short-channel effects. In conjunction with Dr. Woo Young Jung while he was a Ph.D. student at The University of Texas at Austin, two prototype implementations of the proposed architecture were designed and fabricated in TSMC 180 nm CMOS and IBM 45 nm Silicon-On-Insulator (SOI) processes. The prototype ADCs demonstrate that the architecture can achieve bandwidths of 5-20 MHz and ∼50 dB SNR with very small area. The first generation ADC core occupies an area of only 0.0275 mm² , while the second generation ADC core occupies 0.0192 mm² . The two prototypes can be categorized as some of the smallestarea modulators in the literature. Second, I analyze the measured results of the prototype ADC chips, and determine the source for the harmonic distortion. I then demonstrate a digital calibration algorithm that sufficiently mitigates the distortion. This calibration approach falls in the general philosophy of digitally-assisted analog systems. In this philosophy, digital calibration and post-correction are favored over traditional analog solutions, in which there is a high cost to the analog solution either in complexity, power, or area. | en |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/2152/31017 | en |
| dc.language.iso | en | en |
| dc.subject | Analog-to-digital converters | en |
| dc.subject | Time-based ADCs | en |
| dc.subject | Delta-sigma modulators | en |
| dc.title | Analog-to-digital converter circuit and system design to improve with CMOS scaling | en |
| dc.type | Thesis | en |
| thesis.degree.department | Electrical and Computer Engineering | en |
| thesis.degree.discipline | Electrical and Computer Engineering | en |
| thesis.degree.grantor | The University of Texas at Austin | en |
| thesis.degree.level | Doctoral | en |
| thesis.degree.name | Doctor of Philosophy | en |