Techniques for advancing value prediction
| dc.contributor.advisor | Lin, Yun Clavin | |
| dc.creator | Joshi, Pawan Balakrishna | |
| dc.creator.orcid | 0000-0002-8634-3367 | |
| dc.date.accessioned | 2019-10-17T22:12:44Z | |
| dc.date.available | 2019-10-17T22:12:44Z | |
| dc.date.created | 2019-05 | |
| dc.date.issued | 2019-05-09 | |
| dc.date.submitted | May 2019 | |
| dc.date.updated | 2019-10-17T22:12:45Z | |
| dc.description.abstract | Sequential performance is still an issue in computing. While some prediction mechanisms such as branch prediction and prefetching have been widely adopted in modern, general-purpose microprocessors, others such as value prediction have not been accepted due to their high area and misprediction overheads. True data dependences form a major bottleneck in sequential performance and value prediction can be employed to speculatively resolve these dependences. Accurate predictors [1] [2] have been shown to provide performance benefits, albeit requiring a large predictor state. We argue that a first step in making value prediction practical is to manage the metadata associated with the predictor effectively. Inspired by irregular prefetchers that store their metadata in off-chip memory, we propose the use of an improved prefetching mechanism for value prediction that not only provides performance benefits but also a means to off-load predictor state to the memory hierarchy. We show an average of 5.3% IPC improvements across a set of Qualcomm-provided traces [3]. The result of a static instruction can be predicted by mapping runtime context information to the value produced by the instruction. To that end, existing value predictors either use branch history contexts [2] or value history contexts [1] to make predictions. As long histories are needed to achieve high accuracy, these approaches slow down the training time of the predictor, negatively impacting coverage. We identify that branch and value histories both provide distinct advantages to a value predictor, and therefore combine them in a novel predictor design called the Relevant Context-based Predictor (RCP) that maintains high accuracy while improving training time. We show an average of 38% speedup over a baseline that performs no value prediction on the Qualcomm-provided traces, compared to 34% by the previous best. | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | https://hdl.handle.net/2152/76223 | |
| dc.identifier.uri | http://dx.doi.org/10.26153/tsw/3312 | |
| dc.language.iso | en | |
| dc.subject | Value prediction | |
| dc.subject | Processors | |
| dc.subject | Single-thread | |
| dc.subject | Speculation | |
| dc.subject | Relevant context | |
| dc.subject | CVP | |
| dc.subject | Divergence, Metadata | |
| dc.subject | Off-chip | |
| dc.subject | Prefetching | |
| dc.title | Techniques for advancing value prediction | |
| dc.type | Thesis | |
| dc.type.material | text | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | The University of Texas at Austin | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science in Engineering |
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