Data-dependent cycle-accurate power modeling of RTL-level IPs using machine learning

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dc.contributor.advisorGerstlauer, Andreas, 1970-
dc.creatorSrour, Malek
dc.date.accessioned2018-08-07T15:56:34Z
dc.date.available2018-08-07T15:56:34Z
dc.date.created2018-05
dc.date.issued2018-05-03
dc.date.submittedMay 2018
dc.date.updated2018-08-07T15:56:35Z
dc.description.abstractIn a chip design project, early design planning has a strong impact on the schedule and the cost of design. Power estimation is part of early design planning, and it greatly affects design decisions. Power modeling performed at a high level of abstraction is fast but inaccurate due to lack of circuit switching activity information. By contrast, power modeling performed at a low level of abstraction is more accurate as the synthesized circuit synthesis is known, but this simulation is typically slow. This report explores a power modeling approach performed at register transfer level (RTL). It exploits machine learning models in order to have a fast yet relatively accurate cycle-by-cycle power estimation. The approach is data-dependent, where cycle-specific models are trained based on the switching activity of signals obtained from RTL simulation and cycle-by-cycle power values obtained from a reference gate-level simulation of an existing RTL design. Therefore, if any changes are applied to the RTL design, re-training of models is required. The approach aims at obtaining fast yet accurate power predictions for new invocations of a given trained model using signal activity information collected during simulation of the unmodified RTL. At a low level, the complete visibility of signals in a design unintuitively might cause overtraining the model leading to inaccurate estimation. The suggested model employs automatic feature selection in each cycle. Based on the invocations used to train the cycle-by-cycle models, only signals that may switch during a given cycle will be selected as the features for their respective cycle-specific model. The method was tested on an 8-by-8 DCT design and the power estimates were within 6.5% of those from a commercial power analysis tool. This report also simulates and compares the approach of cycle-specific models to the approach of a single global model for all cycles and show that the cycle-specific approach is twice as accurate.
dc.description.departmentElectrical and Computer Engineering
dc.format.mimetypeapplication/pdf
dc.identifierdoi:10.15781/T22F7K85V
dc.identifier.urihttp://hdl.handle.net/2152/65980
dc.language.isoen
dc.subjectCycle-accurate power modeling
dc.subjectPower modeling
dc.subjectMachine learning
dc.subjectChip design
dc.subjectPower estimation
dc.subjectRegister transfer level
dc.subjectAbstraction level
dc.subjectPower predictions
dc.subjectCycle-specific models
dc.titleData-dependent cycle-accurate power modeling of RTL-level IPs using machine learning
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorThe University of Texas at Austin
thesis.degree.levelMasters
thesis.degree.nameMaster of Science in Engineering

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