Improving timing verification and delay testing methodologies for IC designs
| dc.contributor.advisor | Abraham, Jacob A. | en |
| dc.creator | Zeng, Jing | en |
| dc.date.accessioned | 2008-08-28T22:18:12Z | en |
| dc.date.available | 2008-08-28T22:18:12Z | en |
| dc.date.issued | 2005 | en |
| dc.description | text | en |
| dc.description.abstract | The task of ensuring the correct temporal behavior of IC designs, both before and after fabrication, is extremely important. It is becoming even more imperative as the demand for performance increases and process technology advances into the deep sub-micron region. This dissertation tackles the key issues in the timing verification and delay testing methodologies. An efficient methodology is presented to identify false timing paths in the timing verification methodology which utilizes ATPG technique and timing information from an ordered list of timing paths according to the delay information. This dissertation also presents a speed binning methodology which utilizes structural delay tests successfully instead of functional tests. In addition, it establishes a methodology which quantifies the correlation between the timing verification prediction and actual silicon measurement of timing paths. This quantification methodology lays the foundation for further research to study the impact of deep submicron effects on design performance | |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.medium | electronic | en |
| dc.identifier | b60125779 | en |
| dc.identifier.oclc | 62173474 | en |
| dc.identifier.uri | http://hdl.handle.net/2152/1809 | en |
| dc.language.iso | eng | en |
| dc.rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. | en |
| dc.subject.lcsh | Integrated circuits--Design and construction--Methodology | en |
| dc.subject.lcsh | Integrated circuits--Testing | en |
| dc.subject.lcsh | Integrated circuits--Verification | en |
| dc.title | Improving timing verification and delay testing methodologies for IC designs | en |
| dc.type.genre | Thesis | en |
| thesis.degree.department | Electrical and Computer Engineering | en |
| thesis.degree.discipline | Electrical and Computer Engineering | en |
| thesis.degree.grantor | The University of Texas at Austin | en |
| thesis.degree.level | Doctoral | en |
| thesis.degree.name | Doctor of Philosophy | en |