Scalable bus-based on-chip interconnection networks

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dc.contributor.assigneeThe Board of Regents of the University of Texas System
dc.creatorStephen W. Keckler
dc.creatorBoris Robert Grot
dc.date.accessioned2019-10-23T19:33:19Z
dc.date.available2019-10-23T19:33:19Z
dc.date.filed2009-06-19
dc.date.issued2012-11-06
dc.description.abstractThe present disclosure generally relates to systems for routing data across a multinodal network. Example systems include a multinodal array having a plurality of nodes and a plurality of physical communication channels connecting the nodes. At least one of the physical communication channels may be configured to route data from a first node to two or more other destination nodes of the plurality of nodes. The present disclosure also generally relates to methods for routing data across a multinodal network and computer accessible mediums having stored thereon computer executable instructions for performing techniques for routing data across a multinodal network.
dc.description.departmentBoard of Regents, University of Texas System
dc.identifier.applicationnumber12487781
dc.identifier.patentnumber8307116
dc.identifier.urihttps://hdl.handle.net/2152/77174
dc.identifier.urihttp://dx.doi.org/10.26153/tsw/4263
dc.publisherUnited States Patent and Trademark Office
dc.relation.ispartofUniversity of Texas Patents
dc.relation.ispartofUniversity of Texas Patents
dc.rights.restrictionOpen
dc.rights.restrictionOpen
dc.subject.cpcG06F15/7825
dc.subject.uspc370/389
dc.subject.uspc709/238
dc.subject.uspc712/11
dc.subject.uspc712/220
dc.titleScalable bus-based on-chip interconnection networks
dc.typePatent

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