Testing of delay lines in synchronizers

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dc.contributor.advisorAbraham, Jacob A.
dc.creatorDuvvuri, Soumya
dc.date.accessioned2022-08-03T23:21:27Z
dc.date.available2022-08-03T23:21:27Z
dc.date.issued2005-05-21
dc.description.abstractWith increasing complexity and speed of System-on-chip (SOC) designs, asynchronous design has become common among digital designers. Synchronous-asynchronous interactions will emerge as a key issue in future SOC designs. This poses test problems due to special modules employed in such interactions called synchronizers. Synchronizers have programmable delay lines, phase comparators along with analog modules like delay locked loops which make them hard to test. The present day solutions overlook testing of these modules which are crucial for the proper working of the synchronizer. This work presents a methodology to test delay lines for stuck-at faults and transition faults which were not considered during testing earlieren_US
dc.description.departmentElectrical and Computer Engineeringen_US
dc.format.mediumelectronicen_US
dc.identifier.urihttps://hdl.handle.net/2152/115136
dc.identifier.urihttp://dx.doi.org/10.26153/tsw/42037
dc.language.isoengen_US
dc.relation.ispartofUT Electronic Theses and Dissertationsen_US
dc.rightsCopyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en_US
dc.rights.restrictionRestricteden_US
dc.subjectSynchronizersen_US
dc.subjectDelay linesen_US
dc.subjectSystem-on-chip designsen_US
dc.titleTesting of delay lines in synchronizersen_US
dc.typeThesisen_US
dc.type.genreThesisen_US
thesis.degree.departmentElectrical and Computer Engineeringen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Texas at Austinen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Science in Engineeringen_US

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