ATTC : addressable-TLB based translation coherence

Heterogeneous memory systems are getting popular, however they face significant challenges from translation coherence overheads from page remappings. Translation coherence, which is typically implemented in software, can consume more than 50% of the runtime for some applications in virtualized platforms. In this thesis, these overheads are investigated for a wide variety of multi-threaded benchmarks and a hardware based coherence scheme – ATTC – Addressable TLB-based Translation Coherence – is proposed. ATTC eliminates almost all of the overheads associated with software-based coherence mechanisms, and overcomes the challenges in existing hardware schemes. ATTC enforces a “point of coherence” uniformly for both guest and host page table updates using an addressable TLB (ATLB) in the DRAM akin to the one in [45]. All this is achieved without requiring any additional metadata in L1, L2 TLBs. An inverse mapping table (INVTBL- present in DRAM) that maps host physical pages to ATLB locations helps to precisely track translations. ATTC scheme is studied in detail for an emerging hybrid memory organization (a mix of DRAM and NVM) and it is shown that ATTC practically eliminates all translation coherence overheads, yielding an average improvement of 35.7% over a baseline software coherence scheme in virtualized environment and 7.4% over the current state-of-the-art hardware scheme - HATRIC [49]. Next, TLB coherence overheads in nested virtualized environments is analyzed and ATTC is extended to work in nested virtualization scenarios