Energy-efficient design techniques for high speed continuous time delta sigma modulators

Continuous Time Delta Sigma Modulators (CTDSMs) with high sampling rates are becoming increasing popular in wideband communication applications. Conventional CTDSMs use operational transconductance amplifier (OTA)-based active RC integrators to realize the loop filter. In addition to being power-hungry, high DC-gain OTAs are difficult to realize in ultra-deep submicron CMOS processes. This dissertation addresses techniques to realize high sampling rate CTDSMs in advanced CMOS processes, without using OTA-based active RC integrators. Instead, the author investigates techniques to implement the loop filter using more energy-efficient, open-loop building blocks, namely passive integrators and passive summers, Gm-C integrators and voltage controlled oscillator (VCO)-based integrators. The efficacy of the proposed techniques is supported by silicon measurement results of three different CTDSMs designs which have been fabricated in 40 nm CMOS. The first part of this dissertation attempts to explore power efficient design techniques for single-bit quantizer based CTDSMs in scaled CMOS processes. A single-bit quantizer is typically implemented as a latched comparator whose outputs regenerate to the supply rails. By deliberately ensuring a small voltage swing at the input of the single-bit quantizer, a large effective gain can be obtained from the quantizer. This helps to significantly relax the DC gain requirements of the loop filter, thereby permitting the use of low DC gain active integrators and even passive integrators within the loop filter. Exploiting this principle, the first segment of this dissertation introduces a 3rd order single-bit quantizer-based CTDSM with a hybrid active-passive loop filter and finite-impulse-response (FIR) DAC. The jitter suppression capability of the FIR DAC is combined with the superior out-of-band quantization noise filtering capability of a passive integrator, thereby enabling the use of an energy efficient Gm-C integrator at the front-end. Most of the DC loop gain is obtained from the single-bit quantizer. The prototype chip has been fabricated in 40 nm CMOS and achieves signal-to-noise-and-distortion-ratio (SNDR), signalto-noise-ratio (SNR) and dynamic range (DR) of 65.6 dB, 66.7 dB and 67.3 dB respectively in a 5 MHz bandwidth at a sampling rate of 1 GS/s. The second section of this dissertation switches gear to exploring low power design techniques for multibit quantizer based CTDSMs using a voltage controlled oscillator (VCO) as the quantizer and integrator. The most common implementation of a VCO based quantizer employs a transconductor (Gm) stage driving a current controlled oscillator (CCO). However, when using such Gm-CCO based quantizers in closed loop CTDSMs at GHz sampling rates, a major challenge is the VCO’s voltage-to-frequency (V-F) parasitic pole, which causes excess loop delay (ELD) and degrades loop stability. To address this challenge, the second segment of this dissertation introduces a high speed closed-loop capacitive-input VCO-based CTDSM using a novel fully differential VCO topology which virtually eliminates its V-F parasitic pole. The mitigation of the parasitic pole is achieved by splitting the VCO’s input transconductor into a set of distributed input transistors. Capacitive input and capacitive DAC result in a very low thermal noise front end, besides ensuring that there is no additional pole caused due to the VCO’s input capacitance. The prototype 1st-order VCO based CTDSM is fabricated in 40 nm CMOS and occupies a core area of 0.02 mm2 while achieving 63.1 dB DR in 480 kHz to 20.48 MHz bandwidth at 1 GS/s. This is the first work to mitigate the parasitic pole in a fully differential VCO, without relying on any additional active circuits. To the authors’ best knowledge, this is also the first work to demonstrate capacitive input in a high speed CTDSM, without using chopping. The capacitive-input CTDSM presented in the previous section had only 1st order quantization noise shaping and hence its in-band performance was limited by quantization noise. Moreover, it could not digitize signals near DC. To address these limitations, the final section of this dissertation introduces a 2nd order VCO-based CTDSM which uses the distributed-input VCO of the previous section as the second stage (back-end) integrator and quantizer. Due to the more aggressive noise shaping, this modulator’s inband performance is dominated by thermal noise, resulting in a significantly better measured power efficiency (figure-of-merit). Since the modulator has a resistive input, it can digitize signals from near DC. The combination of a GmC integrator and a resistor DAC yields a low-power front-end. The loop filter uses a capacitive-π network to break the constraint between the size of the modulator’s inner capacitive DAC and the factor by which the front-end GmC integrator is impedance scaled. This, in turn, helps to significantly reduce both analog and digital power. The prototype chip has been fabricated in 40 nm CMOS and achieves SNDR, SNR and DR of 71.8 dB, 72.9 dB and 74.5 dB respectively in a 10 MHz bandwidth at 655 MS/s, yielding an SNDR-based Walden figure-of-merit (FoM) of 45.6 fJ/step