A new approach to partial product reduction in multipliers

A multiplier is one of the key hardware components in most digital systems, such as microprocessors, digital signal processing (DSP), and finite impulse response (FIR) filters. It often lies on the critical delay path, having a significant impact on the overall performance of a system. Consequently, it provides significant opportunities for improvements to the design. Generally, multiplication can be divided into three basic steps: partial product formation (PPF), partial product reduction (PPR) and partial product summation (PPS). The PPR step is the most power and time consuming, and is therefore the main focus of this research effort. This thesis explores several circuit level techniques for improving the efficiency during the PPR step, by replacing half adders (HA) and full adders (FA) with more complex multiple bit adders. Two different approaches of implementing these adders have been developed: one is to use short adders (4-bit wide and below) and the other is to use long adders. The use of these approaches leads to fewer reduction stages, which leads to a more efficient multiplier design. Based on these techniques, several multipliers of various lengths have been designed using carry look-ahead adder (CLA) and Kogge-Stone adder (KSA), and implemented in a 45nm process technology. The long CLA based multiplier offers the most performance improvement in terms of area and power consumption, while maintaining the same delay as a Dadda multiplier [6]