Monolithic integration of crystalline oxides on silicon and germanium using atomic layer deposition
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Inside your microelectronic devices there are up to a billion transistors working in flawless operation. Silicon has been the workhorse semiconductor used for the transistor; however, there must be a transition to materials other than silicon, such as germanium, with future device sizes. In addition, new dielectric oxide materials are needed. My research has examined a type of crystalline oxide, known as a perovskite, which is selected for its ability to bond chemically to Si and Ge, and eliminate the electrical defects that affect performance. Many perovskite oxides are lattice-matched to the Si (001) and Ge (001) surface spacing, enabling heteroepitaxy. To date, the majority of research on crystalline oxides integrated with semiconductors has been based on strontium titanate, SrTiO3, epitaxially grown on Si (001) by molecular beam epitaxy. Alternative low-temperature growth methods, such as atomic layer deposition (ALD), offer both practical and economic benefits for the integration of crystalline oxides on semiconductors. My initial research informed the broader community that four unit cells (~1.5 nm) of SrTiO3 are required to enable heteroepitaxy on Si. The research has also shown that heteroepitaxial layers can be monolithically integrated with Si (001) without the formation of a SiOx interlayer between the Si (001) surface and the SrTiO3 layer because ALD is performed at lower temperatures than are typical for MBE. Thus, a combined MBE-ALD growth technique creates possible advantages in device designs that require the crystalline oxide to be in contact with the Si (001) surface. In recent work, I have demonstrated a method for integrating crystalline oxides directly on Ge by ALD. Germanium is being explored as an alternative channel material due to its higher hole and electron mobilities than Si, potentially enabling device operation at higher speed. This all-chemical growth process is expected to be scalable, is inherently less costly from a manufacturing cost of ownership, and is based on current manufacturing tool infrastructure. The impact of my research will be in continued scaling of device dimensions with novel materials that will provide faster speed and lower power consumption for microelectronic devices.