Incremental placement for modern VLSI design closure

The nature of multiple objectives and incremental design process for modern VLSI design closure demands advanced incremental placement techniques. In this dissertation, I proposed several novel incremental placement methods for design closure objectives such as timing, signal integrity, legalization, and total wirelength (TWL). These methods can be applied to any physical synthesis system. First technique is sensitivity based netweighting. The objective is to improve both worst negative slack (WNS) and figure of merit (FOM), defined as the total slack difference compared to a certain slack threshold for all timing end points. It performs incremental global placements with netweights based on comprehensive analysis of the wirelength, slack and FOM sensitivities to the netweight. The experiments show promising results for both stand-alone timing driven placement and physical synthesis afterwards. The second technique is noise map driven two-step incremental placement. The novel noise map is used to estimate the placement impact on coupling noise, which takes into account of coupling capacitance, driver resistance and wire resistance. Guided by this accurate noise map, it performs a two-step incremental placement, i.e. cell inflation and local refinement, to expand regions with high noise impact in order to reduce total noise. Experimental results show significant timing and noise improvement with no wirelength penalty or CPU overhead. The third, yet most promising, technique is diffusion based placement migration, which is the smooth movement of cells in an existing placement to address a variety of post placement design closure issues. This method simulates a diffusion process where cells move from high concentration area to low concentration area. The application on placement legalization shows signifi- cant improvements in wirelength and timing as compared to other commonly used legalization techniques. The fourth technique is the first-do-no-harm detailed placement. It uses a set of pin-based timing and electrical constraints to prevent detailed placement techniques from degrading timing or violating electrical constraints while reducing wirelength. The experimental results show that this detailed placement technique not only reduces TWL, but also significantly improves timing.