Low power sensor readout circuit design for IoT applications

Energy and area-efficient sensor readouts have drawn increasing attention in the integrated circuit design field as the entering of the Internet-of-Things (IoT) era. Small form factor and extended battery life have become critical design targets as important as conventional analog and mixed-signal sensor readout specifications such as noise and dynamic range (DR). Technology advancement has brought extensive benefits to digital circuits, but analog circuits have been facing great design challenges due to the voltage supply and transistor intrinsic gain reduction in advanced processes. This presents a strong need for new design frameworks for sensor readouts that can leverage the properties of CMOS scaling instead of being limited by them. On the other hand, for sensor applications where multiple ADCs are required for multi-channel or parallel signal acquisition, the existence of a large number of ADCs usually causes area and power to grow linearly with the number of ADCs. For those applications, analog compression presents a great potential to become a valuable solution to further improve energy efficiency for sensor readouts on top of the advanced circuit design techniques. To address the challenges brought by the era of IoT, this dissertation explores solutions for IoT sensor readouts from two directions: area-/energy-efficient phase-domain VCO-based sensor readout circuit for single-channel general-purpose sensor interface and compressive sensing (CS) based analog compression scheme and readout circuits for multi-channel sensing scenarios. The first work presents a capacitively-coupled voltage-controlled oscillator (VCO)-based sensor readout featuring a hybrid phase-locked loop (PLL) - [Delta-Sigma] modulator structure. This work aims to propose a solution to the issues of analog sensor readout in advanced processes. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization and dynamic element matching (DEM), much reducing hardware/power compared to existing VCO-based readouts' counting scheme. A low-cost in-cell data weighted averaging (DWA) scheme is presented to enable highly linear tri-level digital-to-analog converter (DAC). Fabricated in 40 nm CMOS, the prototype readout achieves 78 dB SNDR in 10 kHz bandwidth, consuming 4.68 µW and 0.025 mm² active area. With 172 dB Schreier FoM, its efficiency advances state-of-the-art VCO-based readouts by 50 times. The second work presents a 4x compressive CMOS image sensor for always-on operation that achieves an energy efficiency of 51 pJ/pixel, while maintaining high image quality of PSNR > 32dB and SSIM > 0.84. This is enabled by an energy-efficient CS encoder, which replaces a densely populated CS encoding method with a highly sparse pseudo-diagonal one. Since the proposed CS encoder can be implemented with an energy-efficient switched-capacitor matrix multiplier at pixel outputs, data compression is achieved before to pixel digitization, thereby greatly reducing ADC power, data size, and I/O power. The energy efficiency of the image sensor is further improved by incorporating it into dynamic single-slope ADCs. A prototype VGA image sensor consumes only 0.7 mW at 45 fps. The corresponding energy per pixel (51 pJ/pixel) amounts to a 20x improvement over the previous low-energy benchmark on CS image sensors.