Performance enhancing software loop transformations for embedded VLIW/EPIC processors

Software pipelining is a performance enhancing loop optimization technique widely used in optimizing compilers. This technique is particularly effective in the context of multimedia and signal processing embedded applications, since the time critical segments of such applications are typically loops. Although software pipelining can dramatically increase the performance of a large segment of today’s embedded applications market, it has two important potential drawbacks. First, it may lead to a significant increase in code size, and thus, to a costly increase in program memory size requirements. Second, it typically increases register pressure. In the context of register limited embedded processors, such an increase may lead to an increase in spills to memory, and thus, to significant performance degradation. In this research, we studied the difficult cost-performance demands posed by the embedded systems market, and developed effective performance enhancing loop optimization techniques/algorithms that directly take into consideration these two critical cost factors. In this dissertation we propose a novel software pipelining framework suitable for compilers targeting clustered embedded VLIW/EPIC processors. The key difference between our approach and previous approaches is that our proposed software pipelining framework can handle code size constraints along with latency and resource constraints while minimizing the increase in register pressure (register file size requirements) typically incurred by software pipelining. This powerful and unique combination of optimization features allows embedded system designers to perform compiler assisted exploration of "Pareto optimal” points with respect to performance, code size, and register requirements, all important figures of merit for embedded software.