Browsing by Subject "Yield"
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Item 2D memristor reliability and modeling for neuromorphic computing(2023-03-31) Huang, Yifu; Lee, Jack Chung-Yeung; Akinwande, Deji; Banerjee, Sanjay; Dodabalapur, Ananth; Shi, LiTwo-dimensional (2D) materials have been reported to exhibit non-volatile resistive switching (NVRS) phenomenon and applied on memristors or resistive random-access memory (RRAM) devices over the past few decades. Recent research further demonstrates the potential for 2D RRAM devices to be implemented in neuromorphic applications. However, reliability is a major challenge for practical application and industrialization. This dissertation presents the improvement of reliability in 2D material-based memristors and in-depth research in electrical characteristics, failure mechanisms, modeling, and neuromorphic applications. Chapter 2 discusses the reliability improvement of 2D monolayer MoS₂-based memristors by electron irradiation treatment. Sulfur vacancies, the density of which is modified by irradiation dosage, are revealed to be significant in the improvement of yield and endurance. Finite element analysis and Monte Carlo modeling are applied to help understand the role of sulfur vacancies in resistive switching and reliability improvement. In Chapter 3, further optimizations in reliability have been done by introducing sulfurization method in the preparation of MoS₂ films and the fine tune of metal deposition, extending the defect engineering from monolayer to multilayer MoS₂. Intriguing convergence of resistive switching metrics from the statistical measurements is highlighted along with the largely improved endurance performance. An effective switching layer model has been proposed to illustrate the underlying physics of endurance improvement and switching metrics convergence. In Chapter 4, a Monte Carlo modeling tool, which helps visualize the physical process and provides additional insight into the effective switching layer model, is discussed in detail. Transmission electron microscope (TEM) measurements provides experimental support to the model. In Chapter 5, pulse measurements of 2D ReSe₂-based memristors are discussed, demonstrating long-term potentiation and depression (LTP and LTD) behaviors in long-term plasticity programming. A Verilog-A model is proposed based on the multiple-step resistive switching behavior. Further, an artificial neural network (ANN) is trained based on the LTP/LTD parameters from experiments, showing the potential application of 2D memristors. In Chapter 6, the application of the constructed ANN model is discussed by investigating the temperature effect in TaOₓ-based memristors. The simulation results provide additional insights for the designs of potential hardware-based neuromorphic computing applications.Item Automatic semiconductor wafer map defect signature detection using a neural network classifier(2010-12) Radhamohan, Ranjan Subbaraya; Ghosh, Joydeep; El-Hamdi, MohamedThe application of popular image processing and classification algorithms, including agglomerative clustering and neural networks, is explored for the purpose of grouping semiconductor wafer defect map patterns. Challenges such as overlapping pattern separation, wafer rotation, and false data removal are examined and solutions proposed. After grouping, wafer processing history is used to automatically determine the most likely source of the issue. Results are provided that indicate these methods hold promise for wafer analysis applications.Item Techniques to minimize circuitry and improve efficiency for defect tolerance(2013-05) Rab, Muhammad Tauseef; Touba, Nur A.As technology continues to scale to smaller geometries and newer dimensions (3-D), with increasingly complex manufacturing processes, the ability to reliably manufacture 100% defect-free circuitry becomes a significant challenge. While implementing additional circuitry to improve yield is economically justifiable, this thesis addresses the cost of defect tolerance by providing lower cost solutions or alternatively more defect tolerance for the same cost in state-of-the-art ICs, including three-dimensional ICs (3-D ICs). Conventional defect tolerance techniques involve incorporating redundancy into the design. This thesis introduces novel designs to maximize the utility of spare elements with minimal circuitry overhead, thereby improving the yield. One idea proposed is Selective Row Partitioning (SRP), a technique which allows a single spare column to be used to repair multiple defective cells in multiple columns. This is done by selectively decoding the row address bits when generating the select signals for the column multiplexers. This logically segments the spare column allowing it to replace different columns in different partitions of the row address space. All the chips are identical, but fuses are used to customize the row decoding circuitry on a chip-by-chip basis. An implementation procedure and results are presented which show improvement in overall yield at a minimal overhead cost. Moreover, new yield-enhancing design techniques for 3-D ICs are introduced. When assembling a 3-D IC, there are several degrees of freedom including which die are stacked together, in what order, and with what rotational symmetry. This thesis describes strategies for exploiting these degrees of freedom to reduce the cost and complexity of implementing defect tolerance. One strategy is to enable asymmetric repair capability within a 3-D memory stack by exploiting the degree of freedom that the order of the die in the stack can be selected. This technique optimizes the number of fuses, and in some cases, the number of spares as well, required to implement defect tolerance. Another innovative technique is to exploit rotational symmetry of the dies to do implicit reconfiguration to implement defect tolerance. Results show that leakage power and performance overhead for defect tolerance can be significantly reduced by this technique.