Browsing by Subject "Transistor level synthesis"
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Item Transistor level re-synthesis for sub-threshold leakage mitigation(2004-12-18) Sebastine, Antony; Abraham, Jacob A.Metal Oxide Semiconductor (MOS) technology is widely used in digital circuit design today because of the ability to design high speed circuits that consume less power as compared to previous technologies like Bipolar Junction Transistors (BJT). The low power consumption of MOS circuits is primarily because they do not conduct once the output has been established and also when the transistors are in the off state. With each technology generation the frequency of operation of CMOS based chips has increased along with an increase in the number of transistors. However, as transistor geometries reduce, MOS transistors stop behaving like ideal switches and continue to conduct current even when they are off. This is known as leakage current and is becoming an ever increasing contributor to the total power consumed by a chip. Todays competitive market requires fast chip design cycles. This has lead to the creation of a large number of Computer Aided Design (CAD) tools, aiding designers with all aspects of chip design and test. Most of the leakage mitigation schemes used in industry today require a great deal of manual intervention in deciding which portions of the circuit can be suitably modified to reduce leakage without adversely affecting performance. Having a large standard cell library consisting of a number of “tactical cells” optimized for leakage as well as cells of multiple threshold voltages is one way to tackle this problem at the synthesis stage. But there is a limit to the number of cells that can be added to the standard cell library without greatly increasing synthesis time. Besides this, it is also costlier to create a library with many leakage optimized custom cells. This work proposes a framework to automate “transistor stacking” as a method to reduce subthreshold leakage. The discussed methodology is based on a transistor level synthesis scheme proposed earlier for performance optimization. This automated scheme can be used in conjunction with other leakage schemes like “multi-Vt” to further reduce subthreshold leakage