Browsing by Subject "TSV"
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Item Microstructure and processing effects on stress and reliability for through-silicon vias (TSVs) in 3D integrated circuits(2015-05) Jiang, Tengfei; Ho, Paul S.; Huang, Rui; Im, Jang-Hi; Shi, Li; Zhao, Jie-HuaCopper (Cu) Through-silicon via (TSV) is a key enabling element that provides the vertical connection between stacked dies in three-dimensional (3D) integration. The thermal expansion mismatch between Cu and Si induces complex stresses in and around the TSV structures, which can degrade the performance and reliability of 3DICs and are key concerns for technology development. In this dissertation, the effects of Cu microstructure and processing conditions on the stress characteristics and reliability of the TSV structure are studied. First, the stress characteristics of Cu TSV structures are investigated using the substrate curvature method. The substrate curvature measurement was supplemented by microstructure and finite element analyses (FEA) to investigate the mechanisms for the linear and nonlinear stress-temperature behaviors observed for the TSV structure. Implications of the near surface stress on carrier mobility change and device keep-out zone (KOZ) are discussed. Second, via extrusion, an important yield and reliability issue for 3D integration, is analyzed. Synchrotron x-ray microdiffraction technique was introduced for direct measurements of local stress and material behaviors in and around the TSV. Local plasticity near the top of the via was observed which provided direct experimental evidence to support the plasticity mechanism of via extrusion. An analytical model and FEA were used to analyze via extrusion based on local plasticity. Next, the effect of Cu microstructure effect on the thermomechanical behaviors of TSVs is investigated. The contribution from grain boundary and interfacial diffusion on via extrusion and the relaxation mechanisms are discussed. Potential approaches to minimize via extrusion are proposed. Finally, the stress characteristics of 3D die stack structures are studied using synchrotron x-ray microdiffraction. High resolution stress mappings were performed and verified by finite element analysis (FEA). FEA was further developed to estimate the stress effect on device mobility changes and the warpage of the integrated structure.Item Nanometer VLSI design-manufacturing interface for large scale integration(2011-05) Yang, Jae-Seok; Pan, David Z.; Abraham, Jacob; Orshansky, Michael; Liu, Frank; Touba, NurAs nanometer Very Large Scale Integration (VLSI) demands more transistor density to fabricate multi-cores and memory blocks in a limited die size, many researches have been performed to keep Moore's Low in two different ways: 2D geometric shrinking and 3D vertical wafer stacking. For the geometric shrinking, nano patterning with 193nm lithography equipment is one of the most fundamental challenges beyond 22nm while the next-generation lithography, such as Extreme Ultra-Violet (EUV) lithography still faces tremendous challenges for volume production in the near future. As a practical solution, Double Patterning Lithography (DPL) has become a leading candidate for sub-20nm lithography process. Another approach for multi-core integration is 3D wafer stacking with Through Silicon Via (TSV). Computer-Aided-Design (CAD) approaches to enable robust DPL and TSV technology are the main focus of this dissertation. DPL poses new challenges for overlay and layout decomposition. Therefore, overlay induced variation modeling and efficient decomposition for better manufacturability are in great demand. Since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. Our experiments show that the delay variation due to overlay in DPL can be up to 9.1%, and well decomposed layout can reduce the variability. For DPL layout decomposition, we propose a multi-objective and flexible framework for stitch minimization, balanced density, and overlay compensation, simultaneously. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. Additional decomposition constraints for overlay compensation are obtained by Integer Linear Programming (ILP). Robust contact decomposition can be obtained with additional constraints. With these constraints, global decomposition is performed using a modified Fiduccia-Mattheyses (FM) graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures. Three-dimensional integration has new manufacturing and design challenges such as device variation due to TSV induced stress and timing corner mismatch between different stacked dies. Since TSV fill material and silicon have different Coefficients of Thermal Expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. Therefore, the systematic variation due to TSV induced stress should be considered for robust 3D IC design. We propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, a stress contour map with an analytical radial stress model is generated. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relations between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. TSV stress induced timing variations can be as much as 10% for an individual cell. As an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware perturbation could reduce cell delay by up to 14.0% and critical path delay by 6.5% in our test case. Three-dimensional Clock Tree Synthesis (3D CTS) is one of the main design difficulties in 3D integration because clock network is spreading over all tiers. In 3D CTS, timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers in 3D CTS. In addition, mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. Therefore, we propose clock period optimization to consider both timing corner mismatch and TSV induced stress. In our experiments, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with the proposed CTS algorithm. As technology scaling continues toward 14nm and 3D-integration, this dissertation addresses several key issues in the design-manufacturing interface, and proposes unified analysis and optimization techniques for effective design and manufacturing integration.Item Nonlinear optical characterization of advanced electronic materials(2012-08) Lei, Ming, active 2012; Downer, Michael CoffinContinuous downscaling of transistor size has been the major trend of the semiconductor industry for the past half century. In recent years, however, fundamental physical limits to continued downscaling were encountered. In order to overcome these limits, the industry experimented --- and continues to experiment --- with many new materials and architectures. Non-invasive, in-line methods of characterizing critical properties of these structures are in demand. This dissertation develops optical second-harmonic generation (SHG) to characterize performance-limiting defects, band alignment or strain distribution in four advanced electronic material systems of current interest: (1) Hot carrier injection (HCI) is a key determinant of the reliability of ultrathin silicon-on-insulator (SOI) devices. We show that time-dependent electrostatic-field-induced SHG probes HCI from SOI films into both native and buried oxides without device fabrication. (2) Band offsets between advanced high-k gate dielectrics and their substrates govern performance-limiting leakage currents, and elucidate interfacial bond structure. We evaluate band offsets of as-deposited and annealed Al₂O₃, HfO₂ and BeO films with Si using internal photoemission techniques. (3) Epi-GaAs films grown on Si combine the high carrier mobility and superior optical properties of III-V semiconductors with the established Si platform, but are susceptible to formation of anti-phase boundary (APB) defects. We show that SHG in reflection from APB-laden epi-films is dramatically weaker than from control layers without APBs. Moreover, scanning SHG images of APB-rich layers reveal microstructure lacking in APB-free layers. These findings are attributed to the reversal in sign of the second-order nonlinear optical susceptibility [chi]⁽²⁾ between neighboring anti-phase domains, and demonstrate that SHG characterizes APBs sensitively, selectively and non-invasively. (4) 3D integration --- i.e. connecting vertically stacked chips with metal through-Si-vias (TSVs) --- is an important new approach for improving performance at the inter-chip level, but thermal stress of the TSVs on surrounding Si can compromise reliability. We present scanning SHG images for different polarization combinations and azimuthal orientations that reveal the sensitivity of SHG to strain fields surrounding TSVs. Taken together, these results demonstrate that SHG can identify performance-limiting defects and important material properties quickly and non-invasively for advanced MOSFET device applications.Item The role of aquifer storage and recovery (ASR) in sustainbility(2010-12) AlRukaibi, Duaij; McKinney, Daene C.; Maidment, DavidKuwait is an arid country situated at the head of the Arabian Gulf and its water resources can be classified into three significant types: (1) natural (groundwater) and (2) artificial (desalinated sea water and treated wastewater). In the absence of surface water bodies, groundwater constitutes the most important natural water resource in Kuwait with TDS [less than or equal to]10000 mg/L in central and south Kuwait. Only in the north can one find fresh water lenses. Brackish groundwater are used for irrigation, landscaping, construction work, non-potable use in households and mixing with desalinated water up to 10%, to make it potable. The occurrence of usable groundwater is limited to the Kuwait Group and Dammam Formation. Due to over-pumping of groundwater over the last few years, the levels and quality of groundwater are deteriorating. Kuwait is described as the poorest country in terms of water availability (UN World Water-2003). The current rates of water consumption are very high, with 459.6 L/C/d and almost 91 L/C/d for fresh and brackish water, respectively. The water budget of the water resources, represented as percentages is 59% from desalination sea water plants, 32% from groundwater with the possibility to increase the use of this resource and 9% from waste water reuse plants. Although Kuwait does not have any surface water, but it depends on technology to produce water recourses to meet the demand. The best solution for solve the issues of declining water levels and increasing salinity is artificial recharge. Artificial recharge has been applied in Kuwait in different groundwater fields since the 1980s. In addition, the available surface storage capacity of 11.7 Mm³ freshwater is sufficient to meet demand for about 7 days. So, Aquifer storage and recovery (ASR) can be used to store the water in aquifers instead of surface storage. ASR entails storing water in aquifers during wet times and recovering the water from the same well during drought times. Surface storage needs construction resources and vast land. In contrast, storing water in aquifer storage does not need that and it can decrease salinity and keep the water table constant. The water availability for artificial recharge can come from desalination and wastewater plant. The capacity and production of desalination plants are 1.425Mm³/day (525.125Mm³/yr) and 1.31Mm³/day (478.15 Mm³/yr), respectively from 5 stations. The excess capacity is 115000 m³ per day and could reach 290000 m³ per day in the winter season. Wastewater treatment plants produce from 3 plants around 0.337 Mm³/day (123.342 Mm³/yr) and the newest plant (operating by RO system) produces 0.32 Mm³/day (117.12 Mm³/yr) and will reach 0.643 Mm³/day (235.338 Mm³/yr) in 2015. The water produced from wastewater treatment plants has good quality and can be used for irrigation, greening enhancement, landscaping, recreation (artificial river and lakes) and artificial recharge. Also, using water treated for artificial recharge will improve the quality of injected water that has been successfully treated with soil aquifer treatment technology. Groundwater pumping is 200 Mm³ annually and is likely to reach 280 Mm³ in the future. This research will explore and create a database for water resource by GIS software using its tool to select and display suitable areas for ASR operation. Artificial recharge in Kuwait has used the concept of injection and recovery of water in one cycle, while here we will apply the multi-cycle concept to avoid increasing the piezometric head and clogging the porous media. The injected water will be from wastewater treatment plants with a TDS content of less 500 ppm and the TDS of recovered water in each well less than 1500 ppm. Moreover, there are criteria for selecting a domain for artificial recharge, for example, moderate transmissivity, The TDS of the aquifer should not exceed 5000 ppm, and the horizontal and vertical hydraulic gradient should be as small as possible and close to the stations suppler and demand center. The success of artificial recharge will depend on the recovery efficiency (RE) in every cycle which will increase if artificial recharge done in the correct way. The RE increases with a decrease in time between the stopping of injection and the starting of the recovery operation. Aquifer storage and recovery can play an important role as sustainability tool to resolve water resource problems, improving water quality, better than surface water storage since it minimizes construction of new infrastructure and uses that cost to initiate new desalination or waste water plants. At the end of this research we will have demonstrated the concept of the process of ASR including the volume and time for injection and recovery of water in multi-cycles and in different suitable sites.Item The role of aquifer storage and recovery (ASR) technique in sustainability: A case study for Kuwait(Center for Research in Water Resources, University of Texas at Austin, 2010-12) AlRukaibi, Duaij S.; McKinney, Daene C.Item Thermal and mechanical analysis of interconnect structures in 3D stacked packages(2010-05) Wakil, Jamil Abdul; Chen, Shaochen; Ho, Paul S.; Shapiro, Michael; Shi, Li; Sikka, KamalPhysical scaling limits of microelectronic devices and the need to improve electrical performance have driven significant research and development into 3D architecture. The development of die stacks in first level packaging is one of the more viable short-term options for improved performance. Placement of memory die above or below processors in a traditional flip chip C4 package with through-silicon vias (TSVs) has significant benefits in reducing data and power transmission paths. However, with the electrical performance benefits come great thermal and mechanical challenges. There are two key objectives for this work. The first is understanding of the die-die interface resistance, R[subscript dd], composed of the back end of line (BEOL) layers and micro-C4 interconnects. The interfacial resistance between BEOL material layers, the impact of TSVs and the impact of strain on R[subscript dd] are subtopics. The second key objective is the understanding of package thermal and mechanical behavior under operating conditions, such as local thermal disturbances. To date, these topics have not been adequately addressed in the literature. It is found that R[subscript dd] can be affected by TSVs, and that the interfacial contributions predicted by theoretical sub-continuum models can be significantly different than measurements. Using validated finite element models, the significance of the power distribution and R[subscript dd] on the temporal responses of 2D vs. 3D packages is highlighted. The results suggest local thermal hotspots can greatly exacerbate the thermal penalty due to the R[subscript dd] and that no peaks in stress arise in the transient period from power on to power off.Item Thermo-mechanical reliability of 3-D interconnects containing through-silicon-vias (TSVs)(2010-12) Lu, Kuan Hsun; Ho, P. S.; Huang, Rui; Kovar, Desiderio; Ferreira, Paulo J.; Im, Jang-Hi; Zhao, JiehuaThis dissertation focuses on one of the most active research areas in the microelectronics industry: Thermo-mechanical reliability of 3-D interconnects containing through-silicon-vias (TSVs). This study constitutes two parts: 1. Thermal stress measurement on TSVs; 2. Analyses on thermo-mechanical reliability of TSVs. In the first part, a metrology for stress measurement of through-silicon-via (TSV) structures was developed using a bending beam technique. The bending curvature induced by the thermal expansion of a periodic array of Cu TSVs was measured during thermal cycles. The stress components in TSV structures were deduced combining the curvature measurement with a finite-element-analysis (FEA). Temperature-dependent thermal stresses in Cu TSVs and in Si matrix were derived. In the second part, the reliability issues induced by the thermal stresses of TSVs were analyzed from several aspects, including the carrier mobility change in transistors, the interfacial delamination of TSVs, and thermal stress interactions between TSVs. Among them, the mobility change in transistors was found to be sensitive to the normal stresses near the Si wafer surface. The surface area of a high mobility change was defined as the keep-out zone (KOZ) for transistors. FEA simulations were carried out to calculate the area of KOZ surrounding TSVs. The area of KOZ was found to be mainly determined by the channel direction of the transistor as a result of anisotropic piezoresistivity effects. FEA simulations also showed that the KOZ can be controlled by TSV geometry, material selection, etc. Interfacial delamination of TSVs was found to be mainly driven by a shear stress concentration at the TSV/Si interface. Crack driving force for TSV delamination was calculated using FEA simulations, which take into account the magnitude of thermal load, TSV geometry, TSV materials, etc. The results provided a design guideline to improve the TSV delamination problem. In the last, the stress interaction among TSV arrays was examined using a bi-TSV model. In the Cartesian coordinate system, thermal stresses can be intensified or suppressed between TSVs, depending on how TSVs are located. Further analyses suggested that the area of KOZ and the TSV-induced Si cracking can both be improved by optimizing the arrangement of the TSV arrays.Item Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures(2014-12) Zhao, Qiu; Ho, P. S.; Shi, Li; Demcov, Alexander A.; Tsoi, Maxim; Keto, JohnThree-dimensional (3-D) integration is effective to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the device processing, and they have caused serious concerns regarding the thermal-mechanical reliability. Firstly, a semi-analytic approach is introduced to understand stress distributions in TSV structures. This is followed by application of finite element analysis for more accurate prediction of stress behavior according to the real geometry of the sample. The conventional Raman method is used to measure the linear combination of in-plane stress components near silicon top surface Secondly, the limitation of conventional Raman method is discussed: only certain linear combination of in-plane stress, instead of separate value for each stress components, can be obtained. Two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately. Both of them take advantages of different laser polarization profiles to resolve the normal stress components separately based on experimental data. The top-down Raman measurements utilize so called “high NA effect” to obtain additional information, and can resolve all 3 normal stress components. Independent bending beam experiments are used to validate the results from cross-section Raman measurement on the same sample. The correlation between top-down Raman measurement and cross-section Raman measurement are investigated as well. Lastly, as a typical example of 3D IC package, a stack-die memory package is presented. Finite element analysis combined with cross-section Raman measurement and high resolution moiré interferometry were employed to investigate the thermal-mechanical reliability and chip-package interaction of the stack-die memory structure.Item Using IEEE 1500 for wafer testing of TSV Based 3D integrated circuits(2011-12) Ugland, Ryan A.; Touba, Nur; Pan, DavidThe potential end of Moore's law has caused the semiconductor industry to investigate 3D integrated circuits as a way to continue to increase transistor density. Solutions must be put in place to allow each 3D IC die layer to be tested thoroughly on its own at wafer level to unsure adequate yield on assembled 3D devices. This paper details the testability of a 3D implementation of the Open Cores or1200 architecture. IEEE 1500 is used to signi cantly improve wafer level testability of the 3D IC die layers while maintaining a low test pin count requirement.