Browsing by Subject "Switched capacitor"

Now showing 1 - 1 of 1

Wideband receiver and transmitter architectures employing pulse width modulation
(2019-12-06) Kang, Heechai; Gharpurey, Ranjit; Abraham, Jacob; Orshansky, Michael; Kulkarni, Jaydeep; Pullela, Raja
Pulse width modulation (PWM) is an attractive signaling method since it can represent an analog signal while using a discrete-level signal, and is hence more robust to amplitude-noise than a purely analog signal. In addition, PWM can be utilized with switching circuits and thus can benefit from performance and area enhancements that result from process scaling. Receiver and transmitter architectures employing PWM are presented in this work. Architectures to generate high-frequency PWM for representing a wide-bandwidth modulated signal are proposed. A harmonic rejection (HR) receiver that utilizes PWM to implement a sinusoidal local oscillator (LO) with intrinsic HR is demonstrated in Chapter 2. The PWM-LO is employed in a switching mixer. The receiver can be configured to provide additional HR by employing multiphase paths, with appropriate baseband gain coefficients. The PWM generator employs parallel delay-locked loops to implement a three-level natural-sampling dual-edge PWM sinusoidal LO signal, with rejection of the third, fifth and seventh LO harmonics. Gain control using LO-path pulse-width control is demonstrated. The design is implemented in a 40-nm CMOS process. The measured receiver gain with HR is 26.4–30.1 dB in a multi-phase LO configuration and 28–31.8 dB in a single-phase configuration. The double-sideband noise figure at peak gain is 5.8 dB. The design demonstrates worst-case HR3 and HR5 ratios of 47 and 49 dB without calibration for f[subscript LO] = 100 MHz in the multi-phase configuration, with a total power dissipation of 41.1 mW. With calibration, a single-phase peak harmonic rejection ratio (HRR) greater than 73 dB for the third, fifth, and seventh LO harmonics is demonstrated. Gain dependence of the HRR on input signal amplitude is studied. In Chapter 3, a HR downconverter that can provide higher PWM-LO frequencies, in the range of approximately a GHz, is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with switches in the signal-path decreases the sensitivity of the HRR to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3rd and 5th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform. In Chapter 4, a delay-locked loop (DLL) based RF-PWM generator is proposed that can provide RF-PWM in response to broadband signals. The approach can be utilized in a Cartesian transmitter in combination with a switching output stage. The proposed transmitter architecture is verified in a macro-model simulation, using a signal bandwidth of 40 MHz, at a carrier frequency of 2 GHz. In Chapter 5, a Cartesian quadrature power amplifier (QPA) architecture that employs RF-PWM with a switched-capacitor (SC) class-D output stage is described. IQ combining is performed using the SC output stage. Amplitude modulation is performed using RF-PWM, instead of using capacitor ratios in the switched-capacitor combiner, thereby avoiding quantization noise. Outphasing is utilized to synthesize RF-PWM, which alleviates distortion due to narrow pulse-widths in the switching stage. Loss mechanisms in the SC combiner are identified and analyzed. AM-to-AM distortion in the proposed design arises due to resistance variation of the class-D switches. This distortion mechanism is analyzed and demonstrated by means of simulation in a 65-nm CMOS technology. The final part of the thesis (Chapter 6) introduces a Cartesian transmitter that uses of combination of the DLL-based outphasing modulator and switched-capacitor combiner for implementation of a wideband transmitter. An outphasing signal is generated to implement RF-PWM. Full amplitude modulation is achieved while varying the duty-cycle of the RF-PWM generator from 25%-75%, which significantly relaxes the narrow-pulse limitation observed in PWM signaling. The use of the phase detectors synchronized to the two clocks whose phase difference is in quadrature at the PWM frequency enhances the frequency response of the output of the transmitter. The IQ combiner employs a switched-capacitor design, described in Chapter 5. The Cartesian transmitter is implemented in a 65-nm CMOS process. The measured peak output power of the transmitter is 15.5 dBm and the design is verified with digitally-modulated signals with a bandwidth of up to 160 MHz