Browsing by Subject "Standard cell"
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Item FinFET standard cell optimization for performance and manufacturability(2012-05) Zhang, Boyang, 1988-; Pan, David Z.; Sun, NanAs Moore's law continues to 20nm and below, traditional CMOS device faces severe short channel effects. Industry is switching from traditional CMOS to FinFET in order to keep Moore's law alive. Due to the three-dimensional structure of FinFET, many challenges need to be solved. After that, FinFET will finally be able to replace traditional CMOS in the semiconductor industry. This thesis discusses the manufacturing challenges of FinFET. In addressing these challenges, characterization of the FinFET standard cells has been done. The characterization is based on saturation current, leakage current, implantation angle and the average edge placement error at metal one layer. Three design variables, including the metal pitch, the fin pitch and the fin width are optimized to achieve better design quality. Standard cell library which contains combinatorial cells as well as sequential cells are characterized and optimized. Two optimization scenarios are included in the final results. One is performance driven, optimizing the saturation current and the leakage current, while the other is manufacturability driven, optimizing the implantation angle and the average EPE. The optimization results show the tradeoff between performance and manufacturability.Item Lithography variability driven cell characterization and layout optimization for manufacturability(2011-05) Ban, Yong Chan; Pan, David Z.; Abraham, Jacob; Touba, Nur; Lucas, Kevin; Orshansky, MichaelStandard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. This dissertation studies five related research topics in design and manufacturing co-optimization in nanometer standard cells. First, a comprehensive sensitivity metric, which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations, is proposed. The dissertation develops first-order models to compute these sensitivities, and perform robust poly and active layout optimization by minimizing the total delay sensitivity to reduce the delay under the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners. Second, a new equivalent source/drain (S/D) contact resistance model, which accurately calculates contact resistances from contact area, contact position, and contact shape, is proposed. Based on the impact of contact resistance on the saturation current, robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty is performed. Third, this dissertation describes the first layout decomposition methods of spacer-type self-aligned double pattering (SADP) lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two-mask approach using a core mask and a trim mask. This dissertation describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. Fourth, a new cell characterization methodology, which considers a random (line-edge roughness) LER variation to estimate the device performance of a sub-45nm design, is presented. The thesis systematically analyzes the random LER by taking the impact on circuit performance due to LER variation into consideration and suggests the maximum tolerance of LER to minimize the performance degradation. Finally, this dissertation proposes a design aware LER model which claims that LER is highly related to the lithographic aerial image fidelity and the neighboring geometric proximity. With a new LER model, robust LER aware poly layout optimization to minimize the leakage power is performed.Item Standard cell optimization and physical design in advanced technology nodes(2017-05) Xu, Xiaoqing, Ph. D.; Pan, David Z.; Cline, Brian; Orshansky, Michael; Sun, Nan; Touba, Nur A.Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor technology is IC feature-size miniaturization. However, this brings ever-increasing design complexities and manufacturing challenges to the $340 billion semiconductor industry. The manufacturing of two-dimensional layout on high-density metal layers depends on complex design-for-manufacturing techniques and sophisticated empirical optimizations, which introduces huge amounts of turnaround time and yield loss in advanced technology nodes. Our study reveals that unidirectional layout design can significantly reduce the manufacturing complexities and improve the yield, which is becoming increasingly adopted in semiconductor industry [61, 89]. The lithography printing of unidirectional layout can be tightly controlled using advanced patterning techniques, such as self-aligned double and quadruple patterning. Despite the manufacturing benefits, unidirectional layout leads to more restrictive solution space and brings significant impacts on the IC design automation ow for routing closure. Notably, unidirectional routing limits the standard cell pin accessibility, which further exacerbates the resource competitions during routing. Moreover, for post-routing optimization, traditional redundant-via insertion has become obsolete under unidirectional routing style, which makes the yield enhancement task extremely challenging. Regardless of complex multiple patterning and design-for-manufacturing approaches, mask optimization through resolution enhancement techniques remains as the key strategy to improve the yield of the semiconductor manufacturing processes. Among them, Sub-Resolution Assist Feature (SRAF) generation is a very important method to improve lithographic process windows. Model-based SRAF generation has been widely used to achieve high accuracy but it is time-consuming and hard to obtain consistent SRAFs. This dissertation proposes novel CAD algorithms and methodologies for standard cell optimization and physical design in advanced technology nodes, which ultimately reduces the design cycle and manufacturing cost of IC design. First, a standard cell pin access optimization engine is proposed to evaluate the pin accessibility of a given standard cell library. We further propose novel pin access planning techniques and concurrent pin access optimizations to efficiently resolve the routing resource competitions, which generates much better routing solutions than state-of-the-art, manufacturing-friendly routers. To systematically improve the manufacturing yield in the post-routing stage, a global optimization engine has been introduced for redundant local-loop insertion considering advanced manufacturing constraints. Finally, we propose the first machine learning-based framework for fast yet consistent SRAF generation with the high quality of results.