Browsing by Subject "Pulse width modulation"

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Mitigation of harmonic and inter-harmonic effects in nonlinear power converters
(2010-12) Cho, Won Jin; Santoso, Surya
Harmonic distortions are inevitably caused by a rectifier and an inverter due to their inherent nonlinearities. An AC-DC-AC converter, configured by the series connection of a rectifier, DC link, and an inverter, induces harmonic distortions at both AC sides and at the DC link. These harmonics can nonlinearly interact or modulate the fundamental frequencies at the AC sides to cause interharmonic distortions. Harmonic and interharmonic distortions can seriously hamper the normal operation of the power system by means of side effects such as excitation of undesirable electrical and/or mechanical resonances, misoperation of control devices, and so forth. This dissertation presents effective methodologies to mitigate harmonic and interharmonic distortions by applying dithered pulse-width modulated (PWM) signals to a voltage-sourced inverter (VSI) type adjustable speed drive (ASD). The proposed methods are also efficient because the dithering applications are performed on control signals without the need for additional devices. By the help of dithering, the rejection bandwidth of a harmonic filter can be relaxed, which enables a lower-order configuration of harmonic filters. First, this dissertation provides a dithering application on gating signals of a sinusoidal PWM (SPWM) inverter in the simulated VSI-ASD model. The dithering is implemented by adding intentional noise into the SPWM process to randomize rising and falling edges of each pulse in a PWM waveform. As a result of the randomized edges, the periodicity of each pulse is varied, which result in mitigated harmonic tones. This mitigation of PWM harmonics also reduces associated interharmonic distortions at the source side of the ASD. The spectral densities at harmonic and interharmonic frequencies are quanti fied by Fourier analysis. It demonstrates approximately up to 10 dB mitigation of harmonic and interharmonic distortions. The nonlinear relationship between the mitigated interharmonics and harmonics is confirmed by cross bicoherence analysis of source- and DC-side current signals. Second, this dissertation proposes a dithered sigma-delta modulation (SDM) technique as an alternative to the PWM method. The dithering method spreads harmonic tones of the SD M bitstream into the noise level. The noise-shaping property of SDM induces lower noise density near the fundamental frequency. The SDM bitstream is then converted into SDM waveform after zero-order interpolation by which the noise-shaping property repeats at every sampling frequency of the bitstream. The advantages of SDM are assessed by comparing harmonic densities and the number of switching events with those of SPWMs. The dithered SD M waveform bounds harmonic and noise densities below approximately -30 dB with respect to the fundamental spectral density without increasing the number of switching events. Third, this dissertation provides additional validity of the proposed method via hardware experiments. For harmonic assessment, a commercial three-phase inverter module is supplied by a DC voltage source. Simulated PWM signals are converted into voltage waveforms to control the inverter. To evaluate interharmonic distortions, the experimental configuration is extended to a VSI-ASD model by connecting a three-phase rectifier to the inverter module via a DC link. The measured voltage and current waveforms are analyzed to demonstrate coincident properties with the simulation results in mitigating harmonics and interharmonics. The experimental results also provide the efficacy of the proposed methods; the dithered SPWM method effectively mitigates the fundamental frequency harmonics and associated interharmonics, and the dithered SDM reduces harmonics with the desired noise-shaping property.
Voltage-mode controlled synchronous DC-DC buck converter using 0.13[mu] CMOS switches
(2011-12) Wolfe, Brandon Ward; Abraham, Jacob A.; Wang, Xianyao
This report is a study of the effects of a commercial 0.13[mu] process and automotive temperature corners on a synchronous DC-DC buck converter design. The basics of switching converters will be explored with an emphasis on voltage-mode controlled feedback. A Type-III compensation network is designed using transfer function analysis to compensate for the inherent double pole introduced by an LC network. The output of the compensation network will drive a pulse width modulation comparator to vary the duty cycle of the high-side PMOS and low-side NMOS transistor switches. After the synchronous buck converter design was complete, the effect of process and temperature on efficiency, output voltage ripple, inductor peak to peak current, and output voltage load response was examined.
Wideband receiver and transmitter architectures employing pulse width modulation
(2019-12-06) Kang, Heechai; Gharpurey, Ranjit; Abraham, Jacob; Orshansky, Michael; Kulkarni, Jaydeep; Pullela, Raja
Pulse width modulation (PWM) is an attractive signaling method since it can represent an analog signal while using a discrete-level signal, and is hence more robust to amplitude-noise than a purely analog signal. In addition, PWM can be utilized with switching circuits and thus can benefit from performance and area enhancements that result from process scaling. Receiver and transmitter architectures employing PWM are presented in this work. Architectures to generate high-frequency PWM for representing a wide-bandwidth modulated signal are proposed. A harmonic rejection (HR) receiver that utilizes PWM to implement a sinusoidal local oscillator (LO) with intrinsic HR is demonstrated in Chapter 2. The PWM-LO is employed in a switching mixer. The receiver can be configured to provide additional HR by employing multiphase paths, with appropriate baseband gain coefficients. The PWM generator employs parallel delay-locked loops to implement a three-level natural-sampling dual-edge PWM sinusoidal LO signal, with rejection of the third, fifth and seventh LO harmonics. Gain control using LO-path pulse-width control is demonstrated. The design is implemented in a 40-nm CMOS process. The measured receiver gain with HR is 26.4–30.1 dB in a multi-phase LO configuration and 28–31.8 dB in a single-phase configuration. The double-sideband noise figure at peak gain is 5.8 dB. The design demonstrates worst-case HR3 and HR5 ratios of 47 and 49 dB without calibration for f[subscript LO] = 100 MHz in the multi-phase configuration, with a total power dissipation of 41.1 mW. With calibration, a single-phase peak harmonic rejection ratio (HRR) greater than 73 dB for the third, fifth, and seventh LO harmonics is demonstrated. Gain dependence of the HRR on input signal amplitude is studied. In Chapter 3, a HR downconverter that can provide higher PWM-LO frequencies, in the range of approximately a GHz, is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with switches in the signal-path decreases the sensitivity of the HRR to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3rd and 5th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform. In Chapter 4, a delay-locked loop (DLL) based RF-PWM generator is proposed that can provide RF-PWM in response to broadband signals. The approach can be utilized in a Cartesian transmitter in combination with a switching output stage. The proposed transmitter architecture is verified in a macro-model simulation, using a signal bandwidth of 40 MHz, at a carrier frequency of 2 GHz. In Chapter 5, a Cartesian quadrature power amplifier (QPA) architecture that employs RF-PWM with a switched-capacitor (SC) class-D output stage is described. IQ combining is performed using the SC output stage. Amplitude modulation is performed using RF-PWM, instead of using capacitor ratios in the switched-capacitor combiner, thereby avoiding quantization noise. Outphasing is utilized to synthesize RF-PWM, which alleviates distortion due to narrow pulse-widths in the switching stage. Loss mechanisms in the SC combiner are identified and analyzed. AM-to-AM distortion in the proposed design arises due to resistance variation of the class-D switches. This distortion mechanism is analyzed and demonstrated by means of simulation in a 65-nm CMOS technology. The final part of the thesis (Chapter 6) introduces a Cartesian transmitter that uses of combination of the DLL-based outphasing modulator and switched-capacitor combiner for implementation of a wideband transmitter. An outphasing signal is generated to implement RF-PWM. Full amplitude modulation is achieved while varying the duty-cycle of the RF-PWM generator from 25%-75%, which significantly relaxes the narrow-pulse limitation observed in PWM signaling. The use of the phase detectors synchronized to the two clocks whose phase difference is in quadrature at the PWM frequency enhances the frequency response of the output of the transmitter. The IQ combiner employs a switched-capacitor design, described in Chapter 5. The Cartesian transmitter is implemented in a 65-nm CMOS process. The measured peak output power of the transmitter is 15.5 dBm and the design is verified with digitally-modulated signals with a bandwidth of up to 160 MHz