Browsing by Subject "Piezoelectric actuator"
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Item Design and development of an adaptive shape wafer chuck to compensate for wafer surface topography and backside particles(2004-05-22) Ganapathisubramanian, Mahadevan; Sreenivasan, S. V.In this thesis an adaptive shape wafer chuck was developed to address the problems caused due to backside particles and wafer surface irregularities during the lithography process. The Step and Flash Imprint Lithography (SFIL) process has been dealt with in particular and the needs of this process have been considered in deciding the design metrics for the wafer chuck. SFIL is a novel, low-cost approach to patterning nano-scale features for semiconductor applications. This research is essential for the reduction of defects in the features created during lithography and would thus increase the yield that can be achieved. Micro-lithographic systems are employed to create sub-micron and nanoscale features during the processing of semiconductor devices. In such systems, particularly optical lithography, SFIL systems and X-ray lithography systems, control of wafer flatness is critical in order to achieve the desired feature sizes. Wafer flatness in the nanometer range is desirable for sub-micron lithography. The wafer surfaces have surface irregularities measured by the following metrics: Total thickness variation (TTV), Total Indicated reading (TIR), and Local Thickness variation (LTV). These errors along with backside particles affect the flatness of a chucked wafer. This would cause pattern replication errors. The adaptive shape wafer chuck, that has been developed, consists of a pin type thin wafer chuck, mounted on a plurality of piezoelectric actuators that are rigidly attached to a stainless steel base plate. By actuating the piezoelectric actuators based on control algorithms detailed in this thesis, the flatness error can be reduced to less than 200nm, which is preferred for creating semiconductor features in the sub-micron range. The thesis starts with an introduction to optical lithography and next generation lithography (NGL) systems. It states the relevance of the problem for each of these lithography methods and how the proposed design addresses them. Simulations of the design and how it corrects for backside particles and wafer surface irregularities are presented. Simulated results based on real bare wafer data are also used to validate the utility of the design presented in this thesis.