Browsing by Subject "Phase change memory"
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Item Efficient error correcting codes for emerging and high-density memory systems(2019-12) Das, Abhishek (Ph. D. in Electrical and Computer Engineering); Touba, Nur A.; Abraham, Jacob A; Pan, Zhigang; Orshansky, Michael; Bhargava, MuditAs memory technology scales, the demand for higher performance and reliable operation is increasing as well. Field studies show increased error rates at dynamic random-access memories. The high density comes at a cost of more marginal cells and higher power consumption. Multiple bit upsets caused by high energy radiation are now the most common source of soft errors in static random-access memories affecting multiple cells. Phase change memories have been in focus as an attractive alternative to DRAMs due to their low power consumption, lower bit cost and high density. But these memories suffer from various reliability issues. The errors caused by such mechanisms can cause large overheads for conventional error correcting codes. This research addresses the issue of memory reliability under these new constraints due to technology scaling. The goal of the research is to address the different error mechanisms as well as increased error rates while keeping the error correction time low so as to enable high throughput. Various schemes have been proposed such as addressing multiple bit upsets in SRAMs through a burst error correcting code which has a linear increase in complexity as compared to exponential increase for existing methods [Das 18b], as well as a double error correcting code with lower complexity and lower correction time for the increased error rates in DRAMs [Das 19]. This research also addresses limited magnitude errors in emerging multilevel cell memories, e.g. phase change memories. A scheme which extends binary Orthogonal Latin Square codes in presented [Das 17] which utilizes a few bits from each cell to provide protection based on the error magnitude. The issue of write disturbance error in multilevel cells is also addressed [Das 18a] using a modified Reed-Solomon code. The proposed scheme achieves a very low decoding time compared to existing methods through the use of a new construction methodology and a simplified decoding procedure. A new scheme is presented using non-binary Hamming codes which protect more memory cells for the same amount of redundancy [Das 18c] through the use of unused columns in the code space of the design.Item The use of memory state knowledge to improve computer memory system organization(2011-05) Isen, Ciji; John, Lizy Kurian; McKinley, Kathryn S.; Erez, Mattan; Aziz, Adnan; Bhargava, Ravi; Gratz, Paul V.The trends in virtualization as well as multi-core, multiprocessor environments have translated to a massive increase in the amount of main memory each individual system needs to be fitted with, so as to effectively utilize this growing compute capacity. The increasing demand on main memory implies that the main memory devices and their issues are as important a part of system design as the central processors. The primary issues of modern memory are power, energy, and scaling of capacity. Nearly a third of the system power and energy can be from the memory subsystem. At the same time, modern main memory devices are limited by technology in their future ability to scale and keep pace with the modern program demands thereby requiring exploration of alternatives to main memory storage technology. This dissertation exploits dynamic knowledge of memory state and memory data value to improve memory performance and reduce memory energy consumption. A cross-boundary approach to communicate information about dynamic memory management state (allocated and deallocated memory) between software and hardware viii memory subsystem through a combination of ISA support and hardware structures is proposed in this research. These mechanisms help identify memory operations to regions of memory that have no impact on the correct execution of the program because they were either freshly allocated or deallocated. This inference about the impact stems from the fact that, data in memory regions that have been deallocated are no longer useful to the actual program code and data present in freshly allocated memory is also not useful to the program because the dynamic memory has not been defined by the program. By being cognizant of this, such memory operations are avoided thereby saving energy and improving the usefulness of the main memory. Furthermore, when stores write zeros to memory, the number of stores to the memory is reduced in this research by capturing it as compressed information which is stored along with memory management state information. Using the methods outlined above, this dissertation harnesses memory management state and data value information to achieve significant savings in energy consumption while extending the endurance limit of memory technologies.