Browsing by Subject "MOSFETs"
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Item Device characterization and reliability of Dysprosium (Dy) incorporated HfO₂ CMOS devices and its application to high-k NAND flash memory(2010-12) Lee, Tackhwi; Banerjee, Sanjay; Lee, Jack C.; Register, Leonard; Chen, Ray; Ekerdt, JohnDy-incorporated HfO₂ gate oxide with TaN gate electrode nMOS device has been developed for high performance CMOS applications in 22nm node technology. DyO /HfO bi-layer structure shows thin EOT with reduced leakage current and less charge trapping compared to HfO₂. Excellent electrical performance of the DyO-capped HfO₂ oxide n-MOSFET such as lower V[subscript TH], higher drive current, and improved channel electron mobility are reported. DyO/HfO samples also show better immunity for V[subscript TH] instability and less severe charge trapping characteristics. Its charge trapping characteristics, conduction mechanisms and dielectric reliability have been investigated in this work. As an application to memory device, HfON charge trapping layered NAND flash memory is developed and characterized. First, temperature-dependent Dy diffusion and the diffusion-driven Dy dipole formation process are discussed to clarify the origin of V[subscript TH] shift, and eventually modulate the effective work function in Dy-Hf-O/SiO₂ system. The Dy-induced dipoles are closely related to the Dy-silicate formation at the high-k/SiO₂ interfaces since the V[subscript FB] shift in Dy₂O₃ is caused by the dipole and coincides with the Dy-silicate formation. Dipole formation is a thermally activated process, and more dipoles are formed at a higher temperature with a given Dy content. The Dy-silicate related bonding structure at the interface is associated with the strength of the Dy dipole moment, and becomes dominant in controlling the V[subscript FB]/V[scubscript TH] shift during high temperature annealing in the Dy- Hf-O/SiO₂ gate oxide system. Dy-induced dipole reduces the degradation of the electron mobility. Second, to understand the reduced leakage current of the DyO/HfO sample, the effective barrier height of Dy₂O₃ was calculated from FN tunneling models, and the band diagram was estimated. The higher effective barrier height of Dy₂O₃, which is around 2.32 eV calculated from the F-N plot, accounts for the reduced leakage current in Dy incorporated HfO₂ nMOS devices. The lower barrier height of HfO₂ result in increased electron tunneling currents enhanced by the buildup of hole charges trapped in the oxide, which causes a severe increase of stress-induced leakage current (SILC), leading to oxide breakdown. However, the increased barrier height in Dy incorporated HfO₂ inhibits a further increase of the electron tunneling from the TaN gate, and trapped holes lessen the hole tunneling currents, resulting in a negligible SILC. The lower trap generation rate by the reduced hole trap density and the reduced hole tunneling of the Dy-doped HfO₂ dielectric demonstrates the high dielectric breakdown strength by weakening the charge trapping and defect generation during the stress. Based on these fundamental studies of the dielectric breakdown, modeling of time-dependent dielectric breakdown (TDDB) was done. The intrinsic TDDB of the Dy-doped HfO₂ gate oxide having 1 nm EOT is characterized by the progressive breakdown (PBD) model. At high temperature, the PBD becomes severe, since thermal energy causes carrier hopping between the localized weak spots. The voltage acceleration factor derived from the power law shows a realistic prediction in comparison with those from the 1/E model. The increase of the voltage acceleration factor at lower stress voltage is due to the lower trap generation rate in Dy- incorporated HfO₂. This voltage acceleration factor can be easily extended to include temperature dependency, and the effective activation energy derived from the power law is voltage dependent. Lastly, I studied the device characteristics of thin HfON charge-trap layer nonvolatile memory in a TaN/Al₂O₃/HfON/SiO₂/p-Si (TANOS) structure. A large memory window and fast erase speed, as well as good retention time, were achieved by using the NH₃ nitridation technique to incorporate nitrogen into the thin HfO₂ layer, which causes a high electron-trap density in the HfON layer. The higher dielectric constant of the HfON charge-trap layer induces a higher electric field in the tunneling oxide at the same voltage compared to non-nitrided films and, thus, creates a high Fowler-Nordheim (FN) tunneling current to increase the erase and programming speed. The trap-level energy in the HfON layer was calculated by using an amphoteric model.Item Germanium and epitaxial Ge:C devices for CMOS extension and beyond(2011-08) Jamil, Mustafa; Banerjee, Sanjay; Colombo, Luigi; Register, Leonard F.; Tutuc, Emanuel; Tsoi, MaximThis work focuses on device design and process integration of high-performance Ge-based devices for CMOS applications and beyond. Here we addressed several key challenges towards Ge-based devices, such as, poor passivation, underperformance of nMOSFETs, and incompatibility of fragile Ge wafers for mass production. We simultaneously addressed the issues of bulk Ge and passivation for pMOSFETs, by fabricating Si-capped epitaxial Ge:C(C<0.5%) devices. Carbon improves the crystalline quality of the channel, while Si capping prevents GeOx formation, creates a quantum well for holes and thus improves mobility. Temperature-dependent characterization of these devices suggests that Si cap thickness needs to be optimized to ensure highest mobility. We developed a simple approach to grow GeO₂ by rapid thermal oxidation, which provides improved passivation, especially for nMOSFETs. The MOSCAPs with GeO₂ passivation show ~10× lower Dit (~8×10¹¹ cm⁻²eV⁻¹) than that of the HF-last devices. The Ge (111) nMOSFETs with GeO₂ passivation show ~2× enhancement in mobility (~715 cm²V⁻¹s⁻¹ at peak) and ~1.6× enhancement in drive current over control Si (100) devices. For improved n⁺/p junctions, we proposed a simple technique of rapid thermal diffusion from "spin-on-dopants" to avoid implantation damage during junction formation. These junctions show a high ION/IOFF ratio (~10⁵⁻⁶) and an ideality factor of ~1.03, indicating a low defect density, whereas, ion-implanted junctions show higher Ioff (by ~1-2 orders) and a larger ideality factor (~1.45). Diffusion-doped and GeO₂-passivated Ge(100) nMOSFETs show a high ION/IOFF ratio (~10⁴⁻⁵) , a low SS (111 mV/decade), and a high [mu]eff (679 cm²V⁻¹s⁻¹ at peak). Moreover, diffusion-doped Ge (111) nMOSFETs show even higher [mu]eff (970 cm²V⁻¹s⁻¹ at peak) that surpasses the universal Si mobility at low Eeff. For Beyond CMOS devices, we investigated Mn-doped Ge:C-on-Si (100), a novel Si-compatible ferromagnetic semiconductor. The investigation suggests that the magnetic properties of these films depend strongly on crystalline structure and Mn concentration. On a different approach, we developed LaOx/SiOx barrier for Spin-diodes that reduces contact resistance by ~10⁴, compared to Al₂O₃ controls and hence is more conducive for spin injection. These ferromagnetic materials and devices can potentially be useful for novel spintronic devices.Item High performance germanium nanowire field-effect transistors and tunneling field-effect transistors(2010-12) Nah, Junghyo, 1978-; Tutuc, Emanuel, 1974-; Banerjee, Sanjay K.; Lee, Jack C.; Dodabalapur, Ananth; Register, Leonard F.; Shi, LiThe scaling of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) has continued for over four decades, providing device performance gains and considerable economic benefits. However, continuing this scaling trend is being impeded by the increase in dissipated power. Considering the exponential increase of the number of transistors per unit area in high speed processors, the power dissipation has now become the major challenge for device scaling, and has led to tremendous research activity to mitigate this issue, and thereby extend device scaling limits. In such efforts, non-planar device structures, high mobility channel materials, and devices operating under different physics have been extensively investigated. Non-planar device geometries reduce short-channel effects by enhancing the electrostatic control over the channel. The devices using high mobility channel materials such as germanium (Ge), SiGe, and III-V can outperform Si MOSFETs in terms of switching speed. Tunneling field-effect transistors use interband tunneling of carriers rather than thermal emission, and can potentially realize low power devices by achieving subthreshold swings below the thermal limit of 60 mV/dec at room temperature. In this work, we examine two device options which can potentially provide high switching speed combined with reduced power, namely germanium nanowire (NW) field-effect transistors (FETs) and tunneling field-effect transistors (TFETs). The devices use germanium (Ge) – silicon-germanium (Si[subscript x]Ge[subscript 1-x]) core-shell nanowires (NWs) as channel material for the realization of the devices, synthesized using a 'bottom-up' growth process. The device design and material choice are motivated by enhanced electrostatic control in the cylindrical geometry, high hole mobility, and lower bandgap by comparison to Si. We employ low energy ion implantation of boron and phosphorous to realize highly doped contact regions, which in turn provide efficient carrier injection. Our Ge-Si[subscript x]Ge[subscript 1-x] core-shell NW FETs and NW TFETs were fabricated using a conventional CMOS process and their electrical properties were systematically characterized. In addition, TCAD (Technology computer-aided design) simulation is also employed for the analysis of the devices.Item Process integration and performance evaluation of Ge-based quantum well channel MOSFETs for sub-22nm node digital CMOS logic technology(2011-05) Lee, Se-Hoon, 1981-; Banerjee, Sanjay; Lee, Jack C.; Register, Leonard F.; Tutuc, Emanuel; Majhi, PrashantSince metal-oxide-semiconductor (MOS) device was first reported around 1959 and utilized for integrated circuits in 1961, complementary MOS technology has become the mainstream of semiconductor industry. Its performance has been improved based on scaling of dimensions of MOS field-effect-transistors (MOSFET) in accordance with Moore’s law, which states that the density of MOSFETs due to scaling approximately doubles every two years. Entering into sub-100nm regime caused a lot of challenges. Traditional way of scaling no longer provided performance enhancement of individual MOSFETs. Increased channel doping which is required to prevent degradation of device electrostatics from short channel effects caused carrier mobility degradation. New inventions needed to be incorporated to sustain performance enhancement trend with scaling. Implementation of process induced strained Si technology allowed mobility enhancement, and high-K/metal gate instead of conventional poly-Si/SiO2 allowed continuing electrical gate oxide thickness scaling, hence extending the life span of Moore’s law. As we are now moving toward 22nm logic technology and below, new concerns have been rapidly aroused. Controlling power consumption and performance variability are becoming as important as developing scaled devices with enhanced performance. Expandability of strained-Si channel technology via process induced strain also faces increasing complexity from ever tighter gate pitch and difficulties in controlling defect level with the channel stress enhancement techniques. At the same time, long-lasting planar MOSFET architecture also faces serious challenges due to the limits of controlling short channel effects. New paradigms and pathways for future technology seems to be required. As a result, new material sets, new device architectures and concepts are being vigorously explored in the literature. These new trends can be categorized into three groups: MOSFET structure with (non-Si) high mobility channel materials, advanced (non-planar) MOSFET structures, and MOSFET-type structures with new device operation concepts such as tunneling FETs. This dissertation presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology.Item Quantum transport and bulk calculations for graphene-based devices(2010-12) Basu, Dipanjan; Banerjee, Sanjay; Register, Leonard F.; Tutuc, Emanuel; MacDonald, Allan H.; Lee, Jack; Ganguly, SwaroopAs devise sizes approach the nanoscale, novel device geometries and materials are considered, and new types of essential physics becomes important and new physical switching mechanism are considered, and as our intuitive understanding of device behavior is stretched accordingly, increasing first-principles simulation is required to understand and predict device behavior. To this end, initially I worked to capture the richness of the confinement and transport physics in quantum-wire devices. I developed an efficient fully three dimensional atomistic quantum transport simulator within a nearest-neighbor atomistic tight-binding framework. However, I soon adapted this work to the study of transport in graphene mono-layer and bilayer nano-ribbons. Motivated by proposals for use of nano-ribbons to create band gaps in otherwise gapless graphene monolayers, I studied the effects of edge disorder in such graphene nano-ribbon FETs. I found that ribbon widths sufficiently narrow to produce useful bandgaps, would also lead to an extreme sensitivity to ribbon-edge roughness and associated performance degradation and device-to-device variability. Going beyond conventional switching but staying with the graphene material system, to model electron-hole condensation in two graphene monolayers separated by a tunnel dielectric potentially beyond room temperature, I developed a self-consistent atomistic tight-binding treatment of the required interlayer exchange interaction within non-local Hartree-Fock mean-field theory. Such condensation, associated many-body enhanced interlayer current flow, and gate-control thereof is the basis for the beyond-CMOS Bilayer-pseudoSpin Field Effect Transistor (BiSFET) proposed by colleagues. I studied the effect of various system parameters and on interlayer charge imbalance on the strength of the condensate state. I also modeled the critical current, the maximum interlayer current that can be supported by the condensate, its detailed dependence on the nature and strength of the required interlayer bare tunneling and on charge imbalance. The results presented here are expected to be used to refine devices models of the BiSFET, and may serve as guides to experiments to observe such a condensate state.Item A study of electrical and material characteristics of III-V MOSFETs and TFETs with high-[kappa] gate dielectrics(2010-12) Zhao, Han, 1982-; Lee, Jack Chung-Yeung; Banerjee, Sanjay K.; Register, Leonard F.; Tutuc, Emanuel; Goel, NitiThe performance and power scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over three decades. As Si complementary metal-oxide-semiconductor (CMOS) scaling is approaching the physical and optical limits, the emerging technology involves new materials for the gate dielectrics and the channels as well as innovative structures. III-V materials have much higher electron mobility compared to Si, which can potentially provide better device performance. Hence, there have been tremendous research activities to explore the prospects of III-V materials for CMOS applications. Nevertheless, the key challenges for III-V MOSFETs with high-[kappa] oxides such as the lack of high quality, thermodynamically stable insulators that passivate the gate oxide/III-V interface still hinder the development of III-V MOS devices. The main focus of this dissertation is to develop the proper processes and structures for III-V MOS devices that result in good interface quality and high device performance. Firstly, fabrication processes and device structures of surface channel MOSFETs were investigated. The interface quality of In[subscript 0.53]Ga[subscript 0.47]As MOS devices was improved by developing the gate-last process with more than five times lower interface trap density (D[subscript it]) compared to the ones with the gate-first process. Furthermore, the optimum substrate structure was identified for inversion-type In[subscript 0.53]Ga[subscript 0.47]As MOSFETs by investigating the effects of channel doping concentration and thickness on device performance. With the proper process and channel structures, the first inversion-type enhancement-mode In[subscript 0.53]Ga[subscript 0.47]As MOSFETs with equivalent oxide thickness (EOT) of ~10 Å using atomic layer deposited (ALD) HfO₂ gate dielectric were demonstrated. The second part of the study focuses on buried channel InGaAs MOSFETs. Buried channel InGaAs MOSFETs were fabricated to improve the channel mobility using various barriers schemes such as single InP barrier with different thicknesses and InP/InAlAs double-barrier. The impacts of different high-[kappa] dielectrics were also evaluated. It has been found that the key factors enabling mobility improvement at both peak and high-field mobility in In[subscript 0.7]Ga[subscript 0.3]As quantum-well MOSFETs with InP/InAlAs barrier-layers are 1) the epitaxial InP/InAlAs double-barrier confining carriers in the quantum-well channel and 2) good InP/Al₂O₃/HfO₂ interface with small EOT. Record high channel mobility was achieved and subthreshold swing (SS) was greatly improved. Finally, InGaAs tunneling field-effect-transistors (TFETs), which are considered as the next-generation green transistors with ultra-low power consumption, were demonstrated with more than two times higher on-current while maintaining much smaller SS compared to the reported results. The improvements are believed to be due to using the In[subscript 0.7]Ga[subscript 0.3]As tunneling junction with a smaller bandgap and ALD HfO₂ gate dielectric with a smaller EOT.