Browsing by Subject "MOSFET"
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Item Analog model parameter extraction-circuits for process monitoring(2019-05-21) Arora, Manisha; Viswanathan, T.R., doctor of electrical engineering; Dodabalapur, AnanthA method for extracting the three parameters of the well-known level-2 Spice MOSFET-model namely threshold voltage, transconductance parameter, and channel length modulation is presented. Currently circuit design is based on CAD tools using complex model parameters obtained by laborious and expensive methods. While this is essential to design reliable systems on a chip, simpler analog techniques can be used for process monitoring. This work presents simple on-chip analog circuits that can characterize MOSFET just by measuring voltages and currents thus reducing the time and complexity of measurement. For this, on-chip implementation of two parameter extraction circuits are presented. The first circuit is for determining the threshold voltage Vth, and transconductance parameter (k). The second is to determine the channel-length modulation parameter (). These circuits generate voltages or currents proportional to model parameters Vth, k and . Simulation results and measured values from these circuits fabricated using TSMC 180nm process are presented. Results are also compared with accurate model parameters currently available in CAD tools to estimate the level of precision attainable using this method.Item III-V MOSFETs from planar to 3D(2013-08) Xue, Fei, active 2013; Lee, Jack Chung-YeungSi complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuously scaling of its feature size. As scaling is approaching its physical limitations, new materials and device structures are expected. High electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k/metal metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability. A comprehensive study on III-V MOSFETs has been presented here focusing on three areas: 1) III-V/high-k/metal gate stack: material and electrical properties of various high-k dielectrics on III-V substrates have been systematically examined; 2) device architecture: device structures from planar surface channel MOSFETs and buried channel quantum well FETs (QWFETs) to 3D gate-wrapped-around FETs (GWAFETs) and tunneling FETs (TFETs) have been designed and analyzed; 3) fabrication process: process flow has been set up and optimized to build scaled planar and 3D devices with feature size down to 40nm. Potential of high performances have been demonstrated using novel III-V/high-k devices. Effective channel mobility was significantly improved by applying buried channel QWFET structure. Short channel effect control for sub-100nm devices was enhanced by shrinking gate dielectrics, reducing channel thickness and moving from 2D planar to 3D GWAFET structure. InGaAs TFETs have also been developed for ultra-low power application. This research work demonstrates that III-V/high-k/metal MOSFETs with superior device performances are promising candidates for future ultimately scaled logic devices.Item Modeling and design of paralleled SiC MOSFET for multi-chip power module(2022-06-24) Liu, Pengkun; Huang, Alex Q.; Santoso, Surya; Hebner, Robert; Hanson, Alex; Strydom, JohanSilicon carbide (SiC) metal–oxide–semiconductor field effect transistors (MOSFETs) have seen rapid growth in recent years, thanks to its low conduction loss, fast switching speed, and good thermal conductivity. For high power applications, it is necessary to parallel two or more devices in order to achieve the desired current rating, conduction loss, and thermal performance. Traditional single-driver multi-chip module (SDM) requires strong drivers and suffers a lot from parasitic parameter mismatch induced transient current unbalance and intrinsic oscillation. To reduce the thermal imbalance and operation risks, the switching speeds of parallel MOSFETs or MOSFET modules in general are usually slowed with larger gate resistance, at the expense of higher switching loss. Therefore, this solution is not optimal since it indicates a poor utilization of the SiC MOSFET’s intrinsic high-speed capability. The research developed analytical models for the transient current sharing and inherent oscillation for two paralleled SiC MOSFETs’ switching process. The transient current sharing model is developed based on linearized circuit state equations, while the intrinsic oscillation model is based on small-signal equivalent circuits. By using these models, the influences of parasitic parameters are investigated. The optimized gate resistor selection to compensate circuit mismatches is discussed. Based on the studies and models, a 650 V, 300 A double-side cooling GaN HEMT based SDM is designed and fabricated. A better configuration of the multi-driver multi-chip module (MDM) is proposed and the performances are compared. The analytical models provide a fast way to evaluate and optimize the design or approach of any paralleled MOSFET cases. The proposed MDM solution could be a more efficient, more reliable power module design configuration. The parameter influence and comparison results were verified in the experimental tests.Item Novel 3-D IC technology(2014-05) Zhai, Yujia; Banerjee, Sanjay; Willson, C. G. (C. Grant), 1939-For many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).Item Si/Ge heterojunction tunnel FETs for low power applications and junction engineering in germanium MOSFETs for high performance applications(2016-12) Hsu, William, Ph. D.; Banerjee, Sanjay; Tutuc, Emanuel; Register, Leonard F.; Lee, Jack C.; Bonnecaze, Roger T.Power dissipation has become one of the most significant impediments to continued scaling of complementary metal-oxide-semiconductor (CMOS) technology. Two approaches have been proposed for enabling supply power scaling: (i) reduction of subthreshold swing (SS) with novel operation mechanisms, and (ii) increasing of ON-current with high mobility materials or advanced device architectures. In this work, two alternative devices, tunnel field-effect transistors (TFETs) and Ge-channel MOSFETs, are being explored as possible solutions to these two approaches, respectively. TFETs have the potential to achieve a SS steeper than the thermionic emission defined limit of 60 mV/dec at room temperature to which MOSFETs are subject and, thus, enable lower voltage, lower power logic. On the other hand, Ge is promising as the enabler for high mobility channel, offering the potential to further enhance ON-current. The compatibility with conventional Si CMOS manufacturing makes Ge very attractive compared to other high mobility materials (e.g. III-V). In the first part, a Si-technology compatible Si/Ge heterojunction TFET is proposed. The device design utilizes a strained-Si/strained-Ge vertical heterojunction to provide a staggered-gap band alignment with small effective band gap and gate normal tunneling. Performance evaluation by simulation suggests that the device has the potential to be competitive with modern MOSFETs. In addition, device design guidelines in terms of electrostatic control are discussed while considering the quantum effects. In the second part, we focus on source/drain junction engineering for Ge CMOS. For n-type junctions, advanced activation scheme using non-melt sub-millisecond laser spike annealing is utilized to demonstrate excellent diffusion control and high activation level. For p-type junctions, novel BF implantation is shown to offer a higher B activation level and a shallower junction depth in Ge as compared to B and BF2 implantations. The detail diffusion mechanism of B in the presence of F is studied. High performance Ge n-type and p-type diodes are obtained along with significant reduction of contact resistance, and integration in a MOSFET process flow.Item Technology computer aided design and analysis of novel logic and memory devices(2012-08) Hasan, Mohammad Mehedi; Register, Leonard F.; Banerjee, Sanjay K.; Bank, Seth; MacDonald, Allan H.; McDermott, Mark W.Novel logic and memory device concepts are proposed and analyzed. For the latter purpose the commercial technology computer aided design (TCAD) simulators Taurus and Sentaurus Device by Synopsys are used. These simulators allow ready definition of complex device geometries. Moreover, while not all device physics models are state-of-the-art, the wide variety of device physics considered is advantageous here when not all of the critical device physics is known a priori. The initial device concept analyzed was a one transistor (1T), one capacitor (1C) – pseudo-static random access memory (SRAM). Simulations indicate that tri-gate pass-transistors will offer better gate control and reduced leakage, and tri-gate capacitors will offer increased capacitance, making the overall device performance comparable to SRAM. The second device analyzed was a quantum dot non-volatile memory. In principle, such memories become more reliable for a given tunnel oxide thickness by localizing any leaks to individual dots. However, simulations illustrate limits on dot packing density to retain this advantage due to inter-dot tunneling. The final device, proposed and extensively analyzed here, is a novel tunnel field-effect transistor (TFET), the “hetero-barrier TFET” (HetTFET). In complementary metal-oxide-semiconductor (CMOS) logic, while switching power decreases with voltages, standby power increases due to thermionic emission of charge carriers over the source-to-channel barrier in the constituent metal-oxide-semiconductor field-effect transistors (MOSFETs). As a result, CMOS voltage and, thus, power scaling is approaching an impasse. Because TFETs are not subject to thermionic emission, they are being considering as a replacement for MOSFETs. Various materials systems and device geometries have been considered. However, even in simulation, balancing switching and standby power at low voltages while still providing sufficient transconductance for rapid switching has not proven straightforward. HetTFETs are intended to achieve high on-to-off current ratios via a threshold defined by the onset of band overlap, and high ON-state transconductances via tunneling through thin barriers defined by crystal growth, rather than relying on gate-controlled barrier narrowing in whole or part for either purpose as with other designs. Simulations of n and p-channel HetTFETs suggest the possibility of current CMOS-like performance at much lower voltages.