Browsing by Subject "Interconnects"
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Item Polymer-based integrated photonic devices for interconnects(2018-06-19) Pan, Zeyu; Chen, Ray T.; Pan, Zhigang; Ho, Paul S.; Wang, Yaguo; Tao, HuIntegrated photonic devices based on optical waveguides have been extensively studied for various applications, especially the high-speed intra- and inter-chip interconnects. Usually, a waveguide contains a core with high refractive index and cladding with lower refractive index. Among various waveguides, silicon, polymer, and silicon-polymer hybrid devices are the most promising candidates for low cost, small size, light weight, and low power consumption (CSWaP) optical interconnect. Firstly, silicon-based optical devices can be fabricated using CMOS compatible nanofabrication technology, which is already widely used to manufacture integrated circuits. Silicon photonic devices can have very small footprint and enable high density photonic circuits, due to high refractive index contrast. However, one of the intrinsic obstacles is the absence of χ⁽²⁾-nonlinearity in unstrained silicon due to its centrosymmetric crystal structure, making modulating photons on silicon platform a great challenge. Secondly, polymer-based devices have been found very attractive, owing to the advantages of high thermo-optic (TO) or electro-optic (EO) coefficient, high transparency in the telecommunication wavelength windows, and fabrication feasibility over large areas on printed circuit board (PCB) or other kinds of substrates. The roll-to-roll (R2R) compatible imprinting and ink-jet printing for developing polymer-based devices on flexible or rigid substrates enable large-area, light-weight, low-cost optical interconnects. However, due to the low refractive index contrast, the polymer photonic devices always require large footprint. Finally, the silicon-organic hybrid (SOH) platform enables the marriage of the best of these two materials and thus has been receiving substantial attention. In this dissertation, integrated photonic devices based on silicon, polymer, or hybrid platform will be presented. First, high-efficiency quasi-vertical tapers for polymer waveguide based inter-board optical interconnects will be demonstrated. A triangular-shape tapered structure is adopted above the waveguide core to transform a fiber mode into a single mode polymer rib waveguide mode as an optical mode transformer. A coupling loss of 1.79±0.30 dB and 2.23±0.31 dB per coupler for the quasi-TM and quasi-TE mode respectively have been experimentally demonstrated, across the C and L bands (1535 nm – 1610 nm). Then, a reconfigurable thermo-optic polymer switch based true-time-delay network will be analyzed and demonstrated. Thirdly, I will show a novel subwavelength-grating waveguide ring resonator based high-speed modulators, which is the largest bandwidth and the most compact footprint that has been demonstrated for the ring resonators on the silicon-organic hybrid (SOH) platform. Finally, the on-chip time-division multiplexing and de-multiplexing system will be designed and analyzed.Item Scheduling on-chip networks(2009-08) Wu, Xiang; Aziz, AdnanNetworks-on-Chip (NoC) have been proposed to meet many challenges of modern Systems-on-Chip (SoC) design and manufacturing. At the architectural level, a clean separation of computation and communication helps integration and verification. Networking abstraction of the communication infrastructure also promotes reuse and fast development. But the benefit is most visible when it comes to circuit and physical design. Networks can be made sparse and regular and thus facilitate placement and route. It is also much easier to reach timing and power closure as NoC shield communication details away from complicating analysis. Last but not the least, networks are flexible at the design stage and adaptable post-silicon. Many techniques of tackling process variation and interconnect failure can be built upon NoC. However, when interconnects are time multiplexed in a NoC, the network’s performance will deteriorate if it is not scheduled properly. For a wide range of applications, the traffic on the network can be determined before run-time and offline scheduling offers guaranteed performance and enables simple design. We propose a synthesis flow that takes the data flow graph of the application and a network topology as inputs; and outputs an offline schedule that can be deployed directly to the NoC. We analyze the complexity of combinatorial problems that arise from this context and provide efficient heuristics when polynomial time algorithms are not available assuming P [not equal to] NP. Results on LDPC decoding and FFT designs are compared with previous ones. We further apply our findings to parallel shared memories (PSM) and formalize the PSM architecture and its scheduling problem. An efficient heuristic is derived from our algorithm for unbuffered networks. Another application exemplifies how the NoC can be reprogrammed after silicon is back from fab in order to avoid failed interconnects due to process variation. A simple statistical model is studied and the simulation result is rather interesting. We find out that high performance and yield are not always at conflict if we are able to change the network schedule based on silicon diagnosis.Item Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects(2013-05) Wu, Zhuojie; Ho, P. S.The continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.