Browsing by Subject "Integrated circuits--Testing"
Now showing 1 - 5 of 5
- Results Per Page
- Sort Options
Item Improving timing verification and delay testing methodologies for IC designs(2005) Zeng, Jing; Abraham, Jacob A.The task of ensuring the correct temporal behavior of IC designs, both before and after fabrication, is extremely important. It is becoming even more imperative as the demand for performance increases and process technology advances into the deep sub-micron region. This dissertation tackles the key issues in the timing verification and delay testing methodologies. An efficient methodology is presented to identify false timing paths in the timing verification methodology which utilizes ATPG technique and timing information from an ordered list of timing paths according to the delay information. This dissertation also presents a speed binning methodology which utilizes structural delay tests successfully instead of functional tests. In addition, it establishes a methodology which quantifies the correlation between the timing verification prediction and actual silicon measurement of timing paths. This quantification methodology lays the foundation for further research to study the impact of deep submicron effects on design performanceItem New methodology for low power and less test time in VLSI testing(2006) Lee, Il-Soo; Ambler, Anthony P.Recently, the rapid growth of integrated circuit (IC) has brought up many challenges in IC testing industry. The most challenging problems are the overhead of power dissipation, of test data volume, and of test time. These three challenges are expected to get worse as IC gets more complex and the system-on chip (SOC) gets deeper and more embedded. This dissertation addresses these three challenges thoroughly and then offers the solutions to alleviate their seriousness. These solutions are so well shaped that their performance results turn out to be quite impressive and significant. It is proved by the simulation with the various benchmark circuits, ISCAS’85 and ISCAS’89. Furthermore, this dissertation discusses about the future work, some of which are closely related to the present work. The future work deals with new application of the present work, its possible further improvements, and its new investigation in terms of power dissipation, test data volume, and test time.Item Parametric testing, characterization and reliability of integrated circuits(2006) Datta, Ramyanshu; Abraham, Jacob A.This work deals with the problem of parametric failures in Integrated Circuits (ICs), focussing specifically on timing, which is one of the most important parameters in modern ICs. Two approaches to tackling timing violations are explored, the first being efficient timing characterization, involving delay test and debug, to screen out defective parts, and the second, timing oriented adaptive design for variability related failures. Timing violations are a major source of defective silicon for ICs designed in Deep Sub-micron (DSM) technologies. This is because the performance requirements of such ICs are very high, leading to reduced slack margins, and also because defects and variations in process parameters significantly impact their behavior. However, smaller feature sizes and higher levels of integration, which are characteristic of DSM ICs, have severely limited their controllability and observability, hence hindering efficient timing characterization. In vii this work, techniques to enhance controllability and observability for timing characterization of ICs, using novel Design for Test and Design for Debug techniques are presented. In addition to defects, variations in process parameters also impact the behavior of DSM ICs, and can cause a large number of defect free parts to fail the test process and be discarded, leading to reduction in manufacturing yield. An approach for combatting variations is the use of adaptive or variation aware design. In this work, adaptive design techniques with a focus on timing, i.e., performance-optimized adaptive design, are explored. These techniques ensure that adaptation does not cause a chip to violate timing specifications, and also enable a chip to reconfigure itself to reduce or eliminate variability related timing violations, hence enabling parametric reliability in ICs.Item Reliability and test of high-performance integrated circuits(2003) Mohanram, Kartik; Touba, Nur A.As high-density, low-cost, high-performance computing devices become more ubiquitous, there is an increased necessity to address the reliable operation of such systems. Both on-line test (concurrent error detection (CED)) and off-line (manufacturing test) techniques contribute to ensuring high levels of product reliability. The first part of this thesis focuses on techniques for CED in integrated circuits. The goal is to develop techniques for the insertion of CED circuitry at higher levels of design abstraction, as well as techniques that make it easier to absorb the associated overhead costs of CED. Approaches for automated design of logic circuits that meet failure rate requirements while minimizing the impact to area, performance, and power are described. The primary emphasis in this thesis is on reducing the soft error failure rate in integrated circuits (which dominates). The latter part of this thesis focuses on off-line test techniques for high-frequency I/O ports in integrated circuits. A low-cost trigger-based solution to eliminate the problem of non-determinism that may arise due to limitations in tester edge placement accuracy during at-speed functional test of high-speed source synchronous I/O ports is described. An analysis of when the problem of non-determinism becomes significant enough to warrant the implementation of the proposed solution is also provided.Item Test plan generation technique for complex integrated circuits(2002-12) Lee, Songjun; Ambler, Tony