Browsing by Subject "III-V"
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Item Embedded dielectric microstructures in molecular beam epitaxy : high-quality planar coalescence toward enhanced optoelectronic materials(2018-10-29) Ironside, Daniel Joseph; Bank, Seth Robert; Wasserman, Daniel; Li, Xiaoqin (Elaine); Yu, Edward T; Wang, ZhengSeamless integration of embedded dielectric microstructures in III-V crystal growth is a continued area of research due to its numerous high-impact applications. Historically, investigations into embedded dielectric microstructures within existing crystal growth techniques were focused on blocking dislocations at the III-V/dielectric interface in the production of low defect relaxed high mismatched heteroepitaxy. However, recent efforts have broadened the use of embedded dielectric microstructures for enhancement of optoelectronic device functionality and development of monolithic growth schemes toward integrated photonic circuits. The central challenge of embedding dielectric microstructures in III-V materials is achieving single-crystal high-quality planar coalescence within existing conventional III-V crystal growth techniques without defect. While prevalent in the field of III-V crystal growth, solid-source Molecular Beam Epitaxy (MBE) has a well-known "coalescence problem," historically lacking approaches that achieve planar coalescence over dielectric microstructures. Limited coalescence is in large part due to low diffusion of III-adatoms on dielectric surfaces, typically below 300nm, readily forming polycrystalline deposition on dielectric surfaces exceeding this diffusion length. Several solid-source MBE highly-selective growth and lateral epitaxial overgrowth (LEO) growth approaches have been reported; however, none demonstrating complete planar coalescence over dielectric microstructures. In this dissertation, to overcome the "coalescence problem," we demonstrate for the first time a general methodology for an all-MBE growth of high-quality planar coalescence over a variety of embedded dielectric microstructures. Underpinning the approach, we developed a two-stage all-MBE growth approach for GaAs and InAs on (001) substrates, producing highly selective LEO and planarization, returning the growth front to the (001) surface. Characterization of the growth approach demonstrates for the first time an all-MBE approach to planar coalescence. In application of the two-stage all-MBE growth approach towards photonics, we demonstrate enhancement of quantum emitters using buried silica gratings arrays and develop several methodologies for embedded high-contrast photonic materials through self-formed air voids and molded air channel processes. Lastly, in application to high-quality relaxed high mismatch heteroepitaxy, we demonstrate for the first time an all-MBE approach to III-V metamorphic heteroepitaxy, demonstrating threading dislocation reduction in InAs/GaAs metamorphics with high fill factor embedded silica gratings. Thus, from the material presented here, we provide several significant advances to the long-standing challenge of marrying high-quality semiconductor crystal growth with dielectric microstructures, unlocking several high-impact applications, including high-quality material pathways for enhanced quantum emitters and embedded metasurfaces as well as an all-MBE approach toward heterogeneous III-V integration on silicon.Item Graphene and III-V channel metal-oxide-semiconductor field-effect devices for post-Si CMOS applications(2013-12) Ramón, Michael Edward; Banerjee, Sanjay; Akinwande, Deji; Tutuc, Emanuel; Lee, Jack C; Sreenivasan, S. V.To meet the demands for continuous transistor scaling and performance improvements required by the ITRS, there has been a tremendous amount of effort related to alternative high mobility channel materials as potential Si replacements for MOSFET fabrication. Two particularly attractive material systems include III-V substrates and graphene. Thus far, the high trap density which characterizes high-κ dielectrics and the III-V/high-κ dielectric interface remains an obstacle to III-V substrate integration. In a first aspect of this work, charge traps within the gate stack of III-V MOSFETs, as well as at the III-V/dielectric interface, were examined to better understand their impact on III-V device performance. In particular, a pulsed I-V measurement technique was used to assess the impact of fast and slow transient charging effects on various III-V transistors with ALD-deposited Al2O3 gate dielectric. The charge pumping technique was also utilized to determine the density of interface traps, including their energy distribution and position profile, providing further understanding into the nature of traps in the III-V/high-κ system. Graphene has also attracted considerable interest owing to its high intrinsic mobility, large current densities, thermodynamic and mechanical stability. Yet, a primary challenge to the integration of graphene substrates is the lack of high quality, large-area graphene. Thus, in another aspect of this work, large-area graphene was synthesized by CVD of acetylene on Co thin films, and the influence of Co film thickness on graphene synthesis was studied. Resulting graphene films were characterized using Raman spectroscopy and back-gated GFETs were fabricated. Taking advantage of graphene’s intrinsic ambipolar electron-hole symmetry, GFET frequency doublers were fabricated on low-capacitance, single-crystal quartz substrates. GFETs frequency doublers were found to operate beyond their transit frequency (fT), and in the limit of vanishing device non-idealities, their maximum conversion gain was determined to approach a near lossless value. To further understand and improve GFET RF performance, the impact of parasitic resistances was experimentally examined. RF measurements as a function of temperature and modulated access resistance highlight the strong influence of RC on scaled devices, while the impact of RA becomes more evident for devices with large access regions.Item Investigation of electrical and material characteristics of high-k / III-V MOS devices and SiOx ReRAMs(2013-05) Wang, Yanzhen; Lee, Jack Chung-YeungIn the past few decades, Si-based CMOS technology is approaching to its physical quantum limit by scaling down the gate length and gate oxide thickness to achieve higher drive current for low power and high speed application. High k/III-V stack provides an alternative solution because III-V based metal-oxide-semiconductor (MOS) devices have higher drive current due to the higher electron mobility than silicon. Also high k oxides lower the gate leakage current significantly due to larger thickness under the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. The main obstacle for high k/III-V based MOSFETs is the lack of high quality, thermodynamically stable insulators that passivate the interface, which is also the main driving force in the research area of high k/III-V stack. One of the main focuses of this dissertation is developing a fabrication process flow to lower the interface trap density to enhance the performance of MOSFETs with high k oxides on III-V substrates. Also, an emerging memory device with SiO[subscript x] is also developed. This device can be electrically switched between a high-resistance state (HRS, or OFF-state) and a low-resistance state (LRS, or ON-state). Also it shows high potential for next generation nonvolatile memories due to its small cell area, fast write/erase time, low write voltage, good endurance and scalability. The other main focuses of this dissertation is studying the electroforming, set/reset voltages and passivation issue in this resistive random access memory (RRAM or ReRAM). The first part of this dissertation is about lowering the interface trap density of high k/III-V stack by using a thin layer of Al₂O₃ or LaAlO₃. ALD Al₂O₃/HfO₂ bi-layer gate oxide with different Al₂O₃ thickness (0, 5, 10Å) was deposited. Also ALD LaAlO₃/HfO₂ bi-layer gate oxide with different LaAlO₃ thickness (0, 5, 10, 20, 30, 42Å) was deposited. The total EOT of the bi-layer was maintained at ~1.8nm. Also single La[subscript x]Al[subscript 1-X]O (X =0.25, 0.33, 0.5, 0.66, 0.75) gate dielectric with different La doping level was deposited (EOT=2.5±0.4nm). Device characteristics are compared by using different thickness of interfacial layer. The second part of this dissertation is about F incorporation into high k oxide by using SF₆ plasma. The effect of SF₆ plasma treatment of HfO₂ on III-V substrates is demonstrated. Also effect of different plasma power and different treatment time of SF₆ plasma is studied to optimize plasma conditions. High k bilayer (Al₂O₃/HfO₂) is also used to further improve the device performance by better interface passivation with Al₂O₃. HfO₂ gate oxide dielectric is also engineered using SF₆ plasma treatment to incorporate more F. The third part is a study of III-V tunneling FET using In[subscript 0.7]Ga[subscript 0.3]As p-n junction. The device performance with different n doping concentration is compared. Higher n doping concentration will increase the drive current by reducing the tunneling width while too higher n doping concentration results in tunneling in the middle of p-n junction and significantly increase the subthreshold swing. The forth part is the electroforming, set/reset and passivation study of ReRAM device with SiO[subscript x]. Different methods to reduce the electroforming voltage are developed. Set/reset process is also studied and a possible model is proposed to explain the set/ reset process. A new device structure without sidewall edge is studied for passivation and application in air. The final part is the summary of Ph.D work and also suggestions for future work are discussed.Item Nonlinear optical characterization of advanced electronic materials(2012-08) Lei, Ming, active 2012; Downer, Michael CoffinContinuous downscaling of transistor size has been the major trend of the semiconductor industry for the past half century. In recent years, however, fundamental physical limits to continued downscaling were encountered. In order to overcome these limits, the industry experimented --- and continues to experiment --- with many new materials and architectures. Non-invasive, in-line methods of characterizing critical properties of these structures are in demand. This dissertation develops optical second-harmonic generation (SHG) to characterize performance-limiting defects, band alignment or strain distribution in four advanced electronic material systems of current interest: (1) Hot carrier injection (HCI) is a key determinant of the reliability of ultrathin silicon-on-insulator (SOI) devices. We show that time-dependent electrostatic-field-induced SHG probes HCI from SOI films into both native and buried oxides without device fabrication. (2) Band offsets between advanced high-k gate dielectrics and their substrates govern performance-limiting leakage currents, and elucidate interfacial bond structure. We evaluate band offsets of as-deposited and annealed Al₂O₃, HfO₂ and BeO films with Si using internal photoemission techniques. (3) Epi-GaAs films grown on Si combine the high carrier mobility and superior optical properties of III-V semiconductors with the established Si platform, but are susceptible to formation of anti-phase boundary (APB) defects. We show that SHG in reflection from APB-laden epi-films is dramatically weaker than from control layers without APBs. Moreover, scanning SHG images of APB-rich layers reveal microstructure lacking in APB-free layers. These findings are attributed to the reversal in sign of the second-order nonlinear optical susceptibility [chi]⁽²⁾ between neighboring anti-phase domains, and demonstrate that SHG characterizes APBs sensitively, selectively and non-invasively. (4) 3D integration --- i.e. connecting vertically stacked chips with metal through-Si-vias (TSVs) --- is an important new approach for improving performance at the inter-chip level, but thermal stress of the TSVs on surrounding Si can compromise reliability. We present scanning SHG images for different polarization combinations and azimuthal orientations that reveal the sensitivity of SHG to strain fields surrounding TSVs. Taken together, these results demonstrate that SHG can identify performance-limiting defects and important material properties quickly and non-invasively for advanced MOSFET device applications.Item Properties of III-V digital alloys grown by molecular beam epitaxy(2020-08-17) Rockwell, Ann Kathryn; Bank, Seth Robert; Yu, Edward T; Tutuc, Emanuel; Wasserman, Daniel M; Wang, YaguoAvalanche photodiodes (APDs) are widely used in industry due to their internal gain, which arises from impact ionization. Over the past 40+ years, III-V materials have been intensively studied for avalanche photodetectors, driven by applications including optical communications, imaging, quantum information processing, and autonomous vehicle navigation. Below 1.1μm, Si APDs are the current state-of-the-art, while above 4μm, HgCdTe APDs are the best option. However, the difficulties associated with growth and fabrication of these materials have motivated the search for alternatives. Impact ionization is a stochastic process that introduces noise, thereby limiting sensitivity and achievable bandwidths. Intense effort is required to mitigate this noise through the identification of different materials and device structures. The search for new materials has yielded InAs and the Al [subscript x] In [subscript 1-x] As [subscript y] Sb [subscript 1-y] alloy family, both III-V materials, as alternatives to HgCdTe and Si with very low-noise. However, the lack of a consensus on the importance of different fundamental properties for these materials and structures led to a mostly ad hoc exploration of their properties that has yielded limited success in noise mitigation. This dissertation describes an exciting step toward deterministic design of low-noise avalanche photodetector materials by alternating the composition at the monolayer scale. This represents a dramatic departure from previous approaches, which have concentrated on either unconventional compounds/alloys or nanoscale band-engineering. This dissertation will expand upon previous work on AlInAsSb digital alloys and take well-established materials, such as InGaAs and InAlAs, and improve important performance metrics, such as cutoff wavelength and excess noise, by growing them as digital alloys. Several explanations for such properties will also be proposed. Finally, it will be shown that many digital alloys exhibit favorable temperature-stable bandgaps compared with typical III-V semiconductors, offering the possibility of enhancing the temperature response in APDsItem A study of electrical and material characteristics of III-V MOSFETs and TFETs with high-[kappa] gate dielectrics(2010-12) Zhao, Han, 1982-; Lee, Jack Chung-Yeung; Banerjee, Sanjay K.; Register, Leonard F.; Tutuc, Emanuel; Goel, NitiThe performance and power scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over three decades. As Si complementary metal-oxide-semiconductor (CMOS) scaling is approaching the physical and optical limits, the emerging technology involves new materials for the gate dielectrics and the channels as well as innovative structures. III-V materials have much higher electron mobility compared to Si, which can potentially provide better device performance. Hence, there have been tremendous research activities to explore the prospects of III-V materials for CMOS applications. Nevertheless, the key challenges for III-V MOSFETs with high-[kappa] oxides such as the lack of high quality, thermodynamically stable insulators that passivate the gate oxide/III-V interface still hinder the development of III-V MOS devices. The main focus of this dissertation is to develop the proper processes and structures for III-V MOS devices that result in good interface quality and high device performance. Firstly, fabrication processes and device structures of surface channel MOSFETs were investigated. The interface quality of In[subscript 0.53]Ga[subscript 0.47]As MOS devices was improved by developing the gate-last process with more than five times lower interface trap density (D[subscript it]) compared to the ones with the gate-first process. Furthermore, the optimum substrate structure was identified for inversion-type In[subscript 0.53]Ga[subscript 0.47]As MOSFETs by investigating the effects of channel doping concentration and thickness on device performance. With the proper process and channel structures, the first inversion-type enhancement-mode In[subscript 0.53]Ga[subscript 0.47]As MOSFETs with equivalent oxide thickness (EOT) of ~10 Å using atomic layer deposited (ALD) HfO₂ gate dielectric were demonstrated. The second part of the study focuses on buried channel InGaAs MOSFETs. Buried channel InGaAs MOSFETs were fabricated to improve the channel mobility using various barriers schemes such as single InP barrier with different thicknesses and InP/InAlAs double-barrier. The impacts of different high-[kappa] dielectrics were also evaluated. It has been found that the key factors enabling mobility improvement at both peak and high-field mobility in In[subscript 0.7]Ga[subscript 0.3]As quantum-well MOSFETs with InP/InAlAs barrier-layers are 1) the epitaxial InP/InAlAs double-barrier confining carriers in the quantum-well channel and 2) good InP/Al₂O₃/HfO₂ interface with small EOT. Record high channel mobility was achieved and subthreshold swing (SS) was greatly improved. Finally, InGaAs tunneling field-effect-transistors (TFETs), which are considered as the next-generation green transistors with ultra-low power consumption, were demonstrated with more than two times higher on-current while maintaining much smaller SS compared to the reported results. The improvements are believed to be due to using the In[subscript 0.7]Ga[subscript 0.3]As tunneling junction with a smaller bandgap and ALD HfO₂ gate dielectric with a smaller EOT.