Browsing by Subject "Germanium"
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Item Advanced semi-classical Monte Carlo modeling of Si, Ge, InGaAs, and MoS₂ n-channel FETs for novel CMOS(2020-02-03) Bhatti, Aqyan Ahmed; Banerjee, Sanjay; Register, Leonard F.Scaling-down of silicon (Si) based complementary-metal-oxide-semiconductor (CMOS) technologies are approaching material limits. For high-performance applications, high thermal velocity channel materials, such as indium-gallium-arsenide (InGaAs) and germanium (Ge), are viable alternatives to Si to extend the limits of CMOS downscaling. The unique mechanical and electrical properties of two-dimensional atomic crystals, such as single-layer molybdenum disulfide (MoS₂), combined with soft, flexible, and curvilinear substrates, enable new device functionalities and concepts in the field of low-power flexible electronics not achievable with Si channels. While the intrinsic electron mobility of MoS₂ is rather low, strain engineering may provide a pathway for improving electron transport. Silicon, InGaAs, Ge, and MoS₂ n-channel MOSFETs were explored via first-principles computational tools including density functional theory and particle-based ensemble semi-classical Monte Carlo methods to better understand and enable the rational design of end-of-the-roadmap CMOS and potential beyond-CMOS technologies. The impact of contact geometry and transmissivity and gate length scaling on quasi-ballistic nanoscale Si, Ge, and InGaAs n-channel FinFETs was studied. FinFETs with end, saddle/slot, and raised source and drain contacts and the same saddle/slot contact geometry with different gate lengths, according to the projections of industry roadmaps, were simulated. Simulated Si FinFETs exhibited relatively limited degradation in performance due to non-ideal contact transmissivities, more limited sensitivity to contact geometry with non-ideal contact transmissivities, some contact-related advantage for Si 〈110〉 channel devices, and limited sensitivity to gate length scaling. Simulated InGaAs FinFETs were highly sensitive to modeled contact geometry, specific contact resistivity, the band structure model, and gate length scaling. Simulated Ge FinFETs showed substantial degradation due to non-ideal contact transmissivities, sensitivity to gate length scaling, and a large orientation-related advantage for Ge 〈110〉 channel devices. The impact of tensile strain on the intrinsic performance limits of monolayer MoS₂ n-channel MOSFETs was studied. 200 and 15 nm gate length MoS₂ MOSFETs with end contacts subject to different types and amounts of strain were simulated. Simulated MoS₂ MOSFETs displayed improved performance with strain due to lower effective mass and larger inter-valley separation, which is largely reduced due to non-ideal contact transmissivities.Item Chemical modification of nanocolumnar semiconductor electrodes for enhanced performance as lithium and sodium-ion battery anode materials(2014-08) Abel, Paul Robert; Mullins, C. B.Chemical EngineeringItem Chemical vapor deposition of boron carbo-nitride as a potential passivation layer for germanium surfaces(2009-05) Fitzpatrick, Patrick Ryan; Ekerdt, John G.Motivated by the need for a Ge surface passivation layer, chemical vapor deposition of thin (< 10 nm) films of amorphous boron carbo-nitride (BCxNy) on Ge(100) surfaces were studied to assess film continuity, interface bonding, Ge oxidation prevention, and electrical passivation. BCxNy nominally 2.5-5 nm thick continuously covers Ge(100), as determined by ion scattering spectroscopy and two angle resolved x-ray photoelectron spectroscopy (ARXPS) techniques. ARXPS analysis reveals no evidence of an interfacial layer due to elemental intermixing at the BCxNy-Ge(100) interface. High resolution transmission electron microscopy images of HfO₂ / BCxNy / Ge(100) cross-sections reveal abrupt BCxNy-Ge(100) interfaces. XPS was used to track Ge oxidation of BCxNy-covered Ge(100) upon exposure to ambient, 50 °C deionized water, and a 250 °C atomic layer deposition HfO₂ process. If the BCxNy layer is continuous ([greater-than or equal to] ~ 4 nm), the underlying Ge(100) surface is not oxidized despite incorporation of O into BCxNy. Thinner films ([less than or equal to] 3.2 nm) permitted Ge(100) oxidation in each oxidizing environment studied. Ge nanowires with a 5.7 nm BCxNy coating were resistant to oxidation for at least 5 months of ambient exposure. C-V and I-V measurements were made for metal-insulator-semiconductor (MIS) structures fabricated from n-Si(100) and n-Ge(100) wafers passivated with 4.5-5 nm BCxNy. C-rich BC0.61N0.08 films studied up to this point exhibited large amounts of hysteresis and fixed negative charge, so they were abandoned in favor of N-rich BCxNy (0.09 [less than or equal to] x [less than or equal to] 0.15, 0.38 [less than or equal to] y [less than or equal to] 0.52). N-rich BCxNy grown at 275-400 °C showed that lower deposition temperatures resulted in improved electrical characteristics, including decreased hysteresis, lower VFB shift, lower leakage current, and less C-V stretch-out. The electrical improvement is attributed to decreased bulk and interfacial defects in BCxNy deposited at lower temperatures. Even for the lowest growth temperature studied (275 °C), BCxNy-passivated Ge(100) devices had considerable hysteresis and electrical characteristics worsened after a post-metallization anneal. BCxNy-passivated Si(100) devices outperformed similar Ge(100) devices, likely due to the higher interface state densities at the BCxNy-Ge(100) interface associated with the higher relative inertness of Ge(100) to thermal nitridation.Item Crystalline perovskite epitaxial growth on germanium (001) by atomic layer deposition(2017-12) Hu, Shen, Ph. D.; Ekerdt, John G.; Demkov, Alexander A.; Yu, Edward T.; Bonnecaze, Roger T.; Hwang, Gyeong S.Crystalline perovskites (ABO3) have aroused widespread attention in material science due to their multiple properties. This research uses atomic layer deposition (ALD) to achieve perovskite oxides (ABO3) deposition on Ge (001) for gate oxide applications in microelectronics devices. In particular, this work is mainly focused on the study of crystalline Sr-based perovskites SrMO3, where M = Ti, Zr, Hf. In this research work, the mechanism for the initial growth of perovskites on Ge by ALD has been studied. High resolution scanning transmission electron microscopy (STEM) images have shown that both of molecular beam epitaxy (MBE)-grown BaTiO3 films and ALD-grown SrHfO3 films have the same interface structure, which has a 2×1 periodicity and with the alkaline earth metal (AEM) atoms between the Ge dimer rows. This result indicates that the ALD growth proceeds by forming the same Zintl-template layer that is purposely formed in MBE through formation of a 0.5-monolayer (ML) exposure to the AEM. The in situ XPS analysis has shown the same surface core level shift (SCLS) behavior results from half-cycle Sr or Ba precursor dosing on a bare Ge (001) surface as is observed following 0.5 -ML Sr or Ba exposure on Ge by MBE. These observations support the conclusion drawn from the STEM images. Based on the previous study of SrTiO3 (STO) and SrHfO3 (SHO) on Ge (001), there is a trade-off between dielectric constant and leakage current in STO and SHO. This research has also studied SrHfxTi1-xO3 (SHTO) films with different Hf content x to see how composition and lattice constant affected the crystallization behavior. Crystalline SrZrO3 films have also been deposited by ALD on Ge. The C-V and I-V measurements indicate that the SrZrO3 yield the best results for dielectric properties compared to STO, SHO and SHTO. A new combined approach of oxygen plasma pre-treatment, Zintl template formation and atomic deuterium post treatment has been applied on this work to minimize the interface trap density, which has achieved 8.56×1011cm-2eV-1.Item Design, fabrication, and analysis of enhanced mobility silicon germanium transistors(2001-08) Kim, Taehoon; Banerjee, SanjaySilicon-germanium is a very compatible material with silicon. It can improve the performance of the current silicon-based semiconductor devices. A temperature measurement system based on infrared light absorption by the silicon wafer was constructed for a Rapid Thermal Processing Chemical Vapor Deposition system. The details of the temperature measurement system are described here. This system can provide very sensitive temperature measurement for the important 650 – 850 °C range. A relaxed silicon-germanium structure with very smooth surface was grown successfully using this temperature measurement system. A new way to improve the growth of the structure was found. It was also found what the optimum temperature condition for the growth of the structure should be. MOSFETs based on silicon-germanium were fabricated and measured. PMOSFET with a buried channel of silicon-germanium-carbon was fabricated vii and measured to quantify its characteristics. A new method to calculate hole mobility of a buried channel of silicon-germanium-carbon has been proposed. This method requires the low temperature measurement of the device and computer simulation of the device. When this method was used for our PMOSFET, the result successfully revealed hole mobility characteristics of silicon-germanium-carbon. This study also could quantify these characteristics using the well-known Lombardi mobility model for silicon. This device study demonstrated enhanced hole mobility for a certain range of a germanium in silicon-germanium-carbon.Item Electronic and spintronic transport in germanium nanostructures(2014-05) Liu, En-Shao; Tutuc, Emanuel, 1974-The digital information processing system has benefited tremendously from the invention and development of complementary metal-oxide-semiconductor (CMOS) integrated circuits. The relentless scaling of the physical dimensions of transistors has been consistently delivering improved overall circuit density and performance every technology generation. However, the continuation of this trend is in question for silicon-based transistors when quantum mechanical tunneling becomes more relevant; further scaling in feature sizes can lead to increased leakage current and power dissipation. Numerous research efforts have been implemented to address these scaling challenges, either by aiming to increase the performance at the transistor level or to introduce new functionalities at the circuit level. In the first approach, novel materials and device structures are explored to improve the performance of CMOS transistors, including the use of high-mobility materials (e.g. III-V compounds and germanium) as the channel, and multi-gate structures. On the other hand, the overall circuit capability could be increased if other state variables are exploited in the electronic devices, such as the electron spin degree of freedom (e.g. spintronics). Here we explore the potential of germanium nanowires in both CMOS and beyond-CMOS applications, studying the electronic and spintronic transport in this material system. Germanium is an attractive replacement to silicon as the channel material in CMOS technology, thanks to its lighter effective electron and hole mass. The nanowire structures, directly synthesized using chemical vapor deposition, provide a natural platform for multi-gate structures in which the electrostatic control of the gate is enhanced. We present the realization and scaling properties of germanium-silicon-germanium core-shell nanowire n-type, [omega]-gate field-effect transistors (FETs). By studying the channel length dependence of NW FET characteristics, we conclude that the intrinsic channel resistance is the main limiting factor of the drive current of Ge NW n-FETs. Utilizing the electron spins in semiconductor devices can in principle enhance overall circuit performance and functionalities. Electrical injection of spin-polarized electrons into a semiconductor, large spin diffusion length, and an integration friendly platform are desirable ingredients for spin based-devices. Here we demonstrate lateral spin injection and detection in Ge NWs, by using ferromagnetic metal contacts and tunnel barriers for contact resistance engineering. We map out the contact resistance window for which spin transport is observed, manifestly showing the conductivity matching required for spin injection.Item Epitaxial functional oxide integration on germanium(2017-08-14) Ponath, Patrick; Demkov, Alexander A.; Ekerdt, John G.; Lai, Keji; de Lozanne, Alexander; Tsoi, MaximGermanium, with its higher hole and electron mobility is a potential candidate to replace silicon as a channel material in a field effect transistor in the future. The integration of high quality crystalline oxides on semiconductors still remains a challenge due to lattice defects, a lattice constant mismatch as well as a possible thermodynamic instability between the thin film and the substrate. In this work we report the integration of functional oxides on germanium, which exhibit a wide variety of useful physical properties such as ferromagnetism, superconductivity or ferroelectricity which are of high interest for future electronic devices as i.e. for the development of a ferroelectric field-effect transistor. The focus of this thesis lies on the study of the high-[kappa] and ferroelectric material barium titanate, grown on germanium (001) by using an oxide molecular beam epitaxy machine. Further characterization techniques as x-ray diffraction, x-ray reflectivity, x-ray photoelectron spectroscopy, atomic force microscopy and electrical measurements are used to study the properties of the oxide films and to obtain a deeper understanding of their interface qualities with the substrate. This research contributes significantly for the development of a ferroelectric field-effect transistor and oxide heterostructures on germanium in general.Item Epitaxial germanium via Ge:C and its use in non-classical semiconductor devices(2015-12) Mantey, Jason Christopher; Banerjee, Sanjay; Lee, Jack C; Register, Leonard F; Akinwande, Deji; Ferreira, Paulo JThe microelectronics industry has been using Silicon (Si) as the primary material for complementary metal-oxide-semiconductor (CMOS) chip fabrication for more than six decades. Throughout this time, these CMOS devices have gotten exponentially smaller, faster, and cheaper. While new materials and fabrication processes have been slowly added over the years, the CMOS device of today is largely the same as it was decades ago. However, field-effect transistors (FETs) have now scaled so far that Si is approaching physical limits. Thus, new channel materials and new fundamental device structures are being investigated to replace traditional CMOS. Germanium is one of the prime candidates to replace Si in the FET channel, with its increased electron and hole mobilities compared to Si. Perhaps more importantly, it is compatible with the existing Si manufacturing techniques by epitaxially growing thin layers of Ge crystal on the starting Si wafer. Because these two crystals do not share a lattice constant, there will inevitably be crystal defects in the thin Ge layer that can be catastrophic for device functionality. Several approaches have been introduced to reduce defects, but most of them are wastefully thick (>1 um) or require complex manufacturing methods. In this work, we utilize an extremely thin (~10 nm) buffer layer of carbon-doped Ge (Ge:C) to grow Ge and SiGe layers for FET and virtual substrate applications with improved crystalline quality and reduced surface roughnesses. These thin Ge layers not only offer new pathways for MOSFETs, but can also be used in non-classical structures. Semiconductor nanowires (NWs) and tunnel-FETs (TFETs) are two of the most promising device architectures, and both can be used with Ge. This dissertation presents a simulated Si/Ge heterostructure interface TFET that can be fabricated on a virtual substrate made with the Ge:C buffer layer. Detailed analysis on device operation is given. Also in this work is the fabrication process for individually addressable Ge NW-FETs. The NWs offer excellent electrostatic gate control through reduced dimensions and offer another potential pathway for Ge in a post-CMOS world.Item Germanium and silicon nanowires for use in water purification(2022-05-11) Sullivan, William (M.S. in chemical engineering); Korgel, Brain Allan, 1969-Germanium and silicon nanowires present an exciting opportunity for broadening the scope of membrane fouling mitigation research. Germanium nanowires provide a highly effective model system for investigating how to incorporate silicon nanowires into polymeric membranes, while providing relative ease in synthesis and workability compared to silicon nanowires. Silicon nanowires present an exciting area of investigation for fouling mitigation for two main reasons: they can be surface passivated to achieve desired chemical properties and they are photoactive. This work explores how to effectively incorporate germanium nanowires into polymeric membranes as a model to be used for silicon nanowires. Then the integration of silicon nanowires is further explored to determine the most effective methods of silicon nanowire incorporation into polymeric membranes. Successful integration of silicon nanowires into polymeric membrane systems is demonstrated, providing the groundwork for further exploration of the use of nanowires in water purification, specifically for fouling mitigation.Item Germanium MOS devices integrating high-k dielectric and metal gate(2007-05) Bai, Weiping, 1972-; Kwong, Dim-LeeThis dissertation investigates the fabrication and characteristics of the metaloxide-semiconductor (MOS) devices built on germanium substrates integrating HfO2 high-κ dielectric and TaN metal gate electrode. The metal-gate/high-κ/germanium MOS stack, by taking the advantages of the high carrier mobility from the germanium channel and the sub-nm equivalent-oxide-thickness (EOT) scaling capability from the high-κ dielectric and the metal gate electrode, offers a possible solution for the future advanced complementary MOS (CMOS) applications to further boast the transistors’ driving current for faster operation. Due to the unstable and poor-quality natively grown germanium oxide, surface treatment is very critical in germanium device fabrication in order to remove the native oxide and prevent its growth, as well as suppress the interdiffusion across the interface. Several wet cleaning methods and an in situ cleaning technique by Ar anneal have been investigated. Surface passivation techniques, including NH3-based surface nitridation (SN) by forming a GeOxNy layer and silicon interlayer (SiIL) passivation by growing an ultra-thin (several monolayer) silicon layer between the high-κ dielectric and the substrate, have been studied and proved able to improve device performance significantly. Both p- and n-channel germanium transistors have been successfully fabricated. 1.8X enhancement of peak mobility in p-channel and 2.5X in n-channel over the silicon control devices have been achieved. The interface growth mechanism between the germanium substrate and the dielectric layer has been investigated. Two competing processes occurring at the interface determine the formation of the interfacial layer and affect Ge outdiffusion. Substrate dopants are found playing important roles, which causes the variations in the interfacial layer formation on different types of substrates and so on in the electrical properties. The relatively high diffusivity of dopants and germanium atoms in bulk germanium and the induced structural defects near the surface may severely degrade the device performance. This can well explain the very poor performance of the n-channel devices reported recently by several groups. Performance degradation of the germanium devices after thermal anneal, which is resulting from the interdiffusion and germanium oxide desorption, suggests that thermal stability is a concern in high temperature processes and more stable passivation techniques may be required. Long term reliability study indicates that HfO2 dielectric with SN treatment on germanium is robust against TDDB stress and the long term reliability (TDDB) is not a concern for germanium MOS devices.Item Germanium photodetector integrated with silicon-based optical receivers(2006) Huang, Zhihong; Campbell, Joe C.With the development of fiber optics communication systems and optical interconnects, there is an increased demand for low-cost, high-speed, highsensitivity optical receivers. Previously, our group has demonstrated Si photodiodes integrated with CMOS preamplifier circuits. In order to extend the operating wavelength to 1300nm, Ge photodetectors integrated with Si has been studied for Si based optical receivers in this work. Ge has the advantage of compatability with much of Si process technology, as well as the high mobility and large absorption coefficient at 1300 nm. The key challenge for Ge photodetector integrated with Si is the growth of high quality Ge layer on Si. In this work, a successful Ge growth technique has been developed by using a UHV-CVD system. The preliminary integration of Ge photodetector with Si CMOS circuits has also been demonstrated. To further improve the device performance, a SiGe buffer layer technique has been investigated to reduce the dark current of the photodetector. Directly growing Ge on Si generates many dislocations which increase dark current. By using the SiGe buffer layers, many threading dislocations can be “trapped” at the heterojunction interface, thereby reducing the dislocation density in the Ge layer and the photodetector dark current. A backsideilluminated photodetector has been fabricated with the dark current as low as 12 mA/cm2 at 1 V reverse bias, as well as the responsivity of 0.57 A/W and the bandwidth of 8.7 GHz. To improve the speed of these devices, another device with thinner SiGe buffer layers were demonstrated and achieved 21.5 GHz bandwidth at 1.31μm, resulting in a record high efficiency-bandwidth product of 12.9 GHz.Item High performance germanium nanowire field-effect transistors and tunneling field-effect transistors(2010-12) Nah, Junghyo, 1978-; Tutuc, Emanuel, 1974-; Banerjee, Sanjay K.; Lee, Jack C.; Dodabalapur, Ananth; Register, Leonard F.; Shi, LiThe scaling of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) has continued for over four decades, providing device performance gains and considerable economic benefits. However, continuing this scaling trend is being impeded by the increase in dissipated power. Considering the exponential increase of the number of transistors per unit area in high speed processors, the power dissipation has now become the major challenge for device scaling, and has led to tremendous research activity to mitigate this issue, and thereby extend device scaling limits. In such efforts, non-planar device structures, high mobility channel materials, and devices operating under different physics have been extensively investigated. Non-planar device geometries reduce short-channel effects by enhancing the electrostatic control over the channel. The devices using high mobility channel materials such as germanium (Ge), SiGe, and III-V can outperform Si MOSFETs in terms of switching speed. Tunneling field-effect transistors use interband tunneling of carriers rather than thermal emission, and can potentially realize low power devices by achieving subthreshold swings below the thermal limit of 60 mV/dec at room temperature. In this work, we examine two device options which can potentially provide high switching speed combined with reduced power, namely germanium nanowire (NW) field-effect transistors (FETs) and tunneling field-effect transistors (TFETs). The devices use germanium (Ge) – silicon-germanium (Si[subscript x]Ge[subscript 1-x]) core-shell nanowires (NWs) as channel material for the realization of the devices, synthesized using a 'bottom-up' growth process. The device design and material choice are motivated by enhanced electrostatic control in the cylindrical geometry, high hole mobility, and lower bandgap by comparison to Si. We employ low energy ion implantation of boron and phosphorous to realize highly doped contact regions, which in turn provide efficient carrier injection. Our Ge-Si[subscript x]Ge[subscript 1-x] core-shell NW FETs and NW TFETs were fabricated using a conventional CMOS process and their electrical properties were systematically characterized. In addition, TCAD (Technology computer-aided design) simulation is also employed for the analysis of the devices.Item A lithium conducting phase (Li₂Te) can obviate need for nanocrystallites in the lithiation/de-lithiation of Germanium(2015-08) Powell, Emily Janette; Mullins, C. B.; Heller, AdamMainstream rechargeable lithium battery materials research of the past 20 years has focused on nano-particulate materials, where Li⁺-diffusion lengths exceeded at designated cycling rates the particle radii, and where the particles slipped rather than broke upon their expansion and shrinkage in lithiation/de-lithiation cycles. Here we show that in intrinsically rapidly Li⁺-transporting macrocrystalline germanium and even more so in a dispersion of non-cycling Li₂Te in macrocrystalline germanium it is unnecessary to use nanocrystalline materials and that Li₂Te increases the retained capacity at 1C rate after 500 cycles. Dispersions of 10-30 atom % of crystalline GeTe in 90-70 atom % crystalline Ge were synthesized by quenching from the melt followed by high energy ball milling to 1μm-5μm particle size. The particles, as well as similarly made and similarly sized pure Ge particles were incorporated in electrodes, which were galvanostatically lithiated/de-lithiated. In the initial cycle, GeTe is reduced to Li[subscript x]Ge alloys and Li₂Te. In 500 1C cycles of Li[subscript x]Ge de-lithiation/Ge lithiation the capacity of the pure Ge faded more rapidly than that of the Ge electrodes containing Li₂Te, which retained 94-96 % of their initial capacity after 500 cycles at 1C rate.Item Monolithic integration of crystalline oxides on silicon and germanium using atomic layer deposition(2015-05) McDaniel, Martin Douglas; Ekerdt, J. G. (John G.); Demkov, Alexander A; Yu, Edward T; Mullins, Charles B; Manthiram, ArumugamInside your microelectronic devices there are up to a billion transistors working in flawless operation. Silicon has been the workhorse semiconductor used for the transistor; however, there must be a transition to materials other than silicon, such as germanium, with future device sizes. In addition, new dielectric oxide materials are needed. My research has examined a type of crystalline oxide, known as a perovskite, which is selected for its ability to bond chemically to Si and Ge, and eliminate the electrical defects that affect performance. Many perovskite oxides are lattice-matched to the Si (001) and Ge (001) surface spacing, enabling heteroepitaxy. To date, the majority of research on crystalline oxides integrated with semiconductors has been based on strontium titanate, SrTiO3, epitaxially grown on Si (001) by molecular beam epitaxy. Alternative low-temperature growth methods, such as atomic layer deposition (ALD), offer both practical and economic benefits for the integration of crystalline oxides on semiconductors. My initial research informed the broader community that four unit cells (~1.5 nm) of SrTiO3 are required to enable heteroepitaxy on Si. The research has also shown that heteroepitaxial layers can be monolithically integrated with Si (001) without the formation of a SiOx interlayer between the Si (001) surface and the SrTiO3 layer because ALD is performed at lower temperatures than are typical for MBE. Thus, a combined MBE-ALD growth technique creates possible advantages in device designs that require the crystalline oxide to be in contact with the Si (001) surface. In recent work, I have demonstrated a method for integrating crystalline oxides directly on Ge by ALD. Germanium is being explored as an alternative channel material due to its higher hole and electron mobilities than Si, potentially enabling device operation at higher speed. This all-chemical growth process is expected to be scalable, is inherently less costly from a manufacturing cost of ownership, and is based on current manufacturing tool infrastructure. The impact of my research will be in continued scaling of device dimensions with novel materials that will provide faster speed and lower power consumption for microelectronic devices.Item Multispectral gamma-ray analysis using clover detectors with application to uranium fission product analysis(2013-05) Horne, Steven Michael; Landsberger, Sheldon; Jackman, Kevin RichardA high-efficiency gamma-ray counting system has been built at Los Alamos National Laboratory for use in analyzing nuclear forensics samples. This system consists of two clover high-purity germanium detectors and is surrounded by a thallium-doped sodium iodide annulus. Special precautions have been taken to ensure the system has a low background. The system is connected to XIA Pixie-4 fast digitizers and collects data in list-mode. This work is split into two main parts. The first part describes the proper steps and techniques to initialize the settings of a detector system connected to fast digitizers in order to optimize the system for resolution and throughput. The various counting modes for this particular system are described in detail, including the benefits and drawbacks of each mode. Steps are then shown to characterize the system by obtaining efficiency curves for various counting modes and sample geometries. Because of the close counting geometry involved with this system, true-coincidence summing factors must be calculated, and are done so in part by measuring the peak-to-total ratios of the system in its various counting modes across a wide energy range. The dead-time for the system can be complicated due to the multiple inputs of the system. Techniques for calculating the dead-time of multiple-detector systems are discussed. The second part of this work shows the system's usefulness in analyzing nuclear forensics samples, specifically irradiated enriched uranium. Three fission product parent-daughter pairs of different lifetimes are analyzed over a course of six months. The activities of each nuclide are calculated at each time step. Age dating techniques using the parent-daughter pairs are discussed, as well as the detection limits of each nuclide for a range of sample ages. Finally, avenues for further research are presented, as well as potential sources of error or uncertainty for this work.Item Nanostructuring silicon and germanium for high capacity anodes in lithium ion batteries(2012-12) Harris, Justin Thomas; Korgel, Brian Allan, 1969-; Ekerdt, John G.; Hwang, Gyeong S.; Mullins, Charles B.; Stevenson, Keith A.Colloidally synthesized silicon (Si) and germanium (Ge) were explored as high capacity anode materials in lithium ion batteries. a-Si:H particles were synthesized through the thermal decomposition of trisilane in supercritical n-hexane. Precise control over particle size and hydrogen content was demonstrated. Particles ranged in size from 240-1500 nm with hydrogen contents from 10-60 atomic%. Particles with low hydrogen content had some degree of local ordering and were easily crystallized during Raman spectroscopy. The as-synthesized particles did not perform well as an anode material due to low conductivity. Increasing surface conductivity led to enhanced lithiation potential. Cu nanoparticles were deposited on the surface of the a-Si:H particles through a hydrogen facilitated reduction of Cu salts. The resulting Cu coated particles had a lithiation capacity seven times that of pristine a-Si:H particles. Monophenylsilane (MPS) grown Si nanowire paper was annealed under forming gas to reduce a polyphenylsilane shell into conductive carbon. The resulting paper required no binder or carbon additive and achieved capacities of 804 mA h/g vs 8 mA h/g for unannealed wires. Si and Ge heterostructures were explored to take advantage of the higher inherent conductivity of Ge. Ge nanowires were successfully coated with a-Si by thermal decomposition of trisilane on their surface, forming Ge@a-Si core shell structures. The capacity increased with increasing Si loading. The peak lithiation capacity was 1850 mA h/g after 20 cycles – higher than the theoretical capacity of pure Ge. MPS additives created a thin amorphous shell on the wire surfaces. By incubating the wires after MPS addition the shell was partially reduced, conductivity increased, and a 75% increase in lithiation capacity was observed for the nanowire paper. The syntheses of Bi and Au nanoparticles were also explored. Highly monodisperse Bi nanocrystals were produced with size control from 6-18 nm. The Bi was utilized as seeds for the SLS synthesis of Ge nanorods and copper indium diselenide (CuInSe2) nanowires. Sub 2 nm Au nanocrystals were synthesized. A SQUID magnetometer probed their magnetic behavior. Though bulk Au is diamagnetic, the Au particles were paramagnetic. Magnetic susceptibility increased with decreasing particle diameter.Item Semiconductor nanowires : from a nanoscale system to a macroscopic material(2011-12) Holmberg, Vincent Carl; Korgel, Brian Allan, 1969-Semiconductor nanowires are one-dimensional nanoscale systems that exhibit many unique properties. Their nanoscale size can lead to defect densities and impurity populations different than bulk materials, resulting in altered diffusion behavior and mechanical properties. Synthetic methods now support the large-scale production of semiconductor nanowires, enabling a new class of materials and devices that use macroscopic quantities of nanowires. These advances have created an opportunity to fabricate bulk structures which exhibit the unique physical properties of semiconductor nanowires, bridging the properties of a nanoscale system with macroscopic materials. High aspect ratio germanium nanowires were synthesized in supercritical organic solvents using colloidal gold nanocrystal seeds. The nanowires were chemically passivated inside the reactor system using in situ thermal hydrogermylation and thiolation. The chemical stability of the passivated nanowires was studied by exposure to highly corrosive and oxidative environments. Chemical surface functionalization of germanium nanowires was investigated by covalently tethering carboxylic acid groups to the surface, as a general platform for the further functionalization of nanowire surfaces with molecules such as polyethylene glycol. Surface functionalization with dopant-containing molecules was also explored as a potential route for doping nanowires. In addition, static charging was exploited in the development of an electrostatic deposition method for semiconductor nanowires. In situ transmission electron microscopy experiments were conducted on gold-seeded germanium nanowires encapsulated within a volume-restricting carbon shell. A depressed eutectic melting temperature was observed, along with strong capillary effects, and the solid-state diffusion of gold into the crystalline stem of the germanium nanowire, occurring at rates orders of magnitude slower than in the bulk. Copper, nickel, and gold diffusion in silicon nanowires were also investigated. The rate of gold diffusion was found to be a strong function of the amount of gold available to the system. Finally, germanium nanowires were found to exhibit exceptional mechanical properties, with bending strengths approaching that of an ideal, defect-free, perfect crystal, and strength-to-weight ratios greater than either Kevlar or carbon fiber. Macroscopic quantities of nanowires were used to fabricate large sheets of free-standing semiconductor nanowire fabric, and the physical, morphological, and optical properties of the material were investigated.Item Si/Ge heterojunction tunnel FETs for low power applications and junction engineering in germanium MOSFETs for high performance applications(2016-12) Hsu, William, Ph. D.; Banerjee, Sanjay; Tutuc, Emanuel; Register, Leonard F.; Lee, Jack C.; Bonnecaze, Roger T.Power dissipation has become one of the most significant impediments to continued scaling of complementary metal-oxide-semiconductor (CMOS) technology. Two approaches have been proposed for enabling supply power scaling: (i) reduction of subthreshold swing (SS) with novel operation mechanisms, and (ii) increasing of ON-current with high mobility materials or advanced device architectures. In this work, two alternative devices, tunnel field-effect transistors (TFETs) and Ge-channel MOSFETs, are being explored as possible solutions to these two approaches, respectively. TFETs have the potential to achieve a SS steeper than the thermionic emission defined limit of 60 mV/dec at room temperature to which MOSFETs are subject and, thus, enable lower voltage, lower power logic. On the other hand, Ge is promising as the enabler for high mobility channel, offering the potential to further enhance ON-current. The compatibility with conventional Si CMOS manufacturing makes Ge very attractive compared to other high mobility materials (e.g. III-V). In the first part, a Si-technology compatible Si/Ge heterojunction TFET is proposed. The device design utilizes a strained-Si/strained-Ge vertical heterojunction to provide a staggered-gap band alignment with small effective band gap and gate normal tunneling. Performance evaluation by simulation suggests that the device has the potential to be competitive with modern MOSFETs. In addition, device design guidelines in terms of electrostatic control are discussed while considering the quantum effects. In the second part, we focus on source/drain junction engineering for Ge CMOS. For n-type junctions, advanced activation scheme using non-melt sub-millisecond laser spike annealing is utilized to demonstrate excellent diffusion control and high activation level. For p-type junctions, novel BF implantation is shown to offer a higher B activation level and a shallower junction depth in Ge as compared to B and BF2 implantations. The detail diffusion mechanism of B in the presence of F is studied. High performance Ge n-type and p-type diodes are obtained along with significant reduction of contact resistance, and integration in a MOSFET process flow.Item Silicon and germanium battery materials : exploring new structures, surface treatments, and full cell applications(2018-05) Adkins, Emily Renee; Korgel, Brian Allan, 1969-; Mullins, Charles B; Manthiram, Arumugam; Hwang, Gyeong S; Yu, GuihuaLithium ion batteries (LIBs) with higher energy and power density are needed to meet the increasing demands of portable electronic devices, extended-range electric vehicles, and renewable energy storage. Silicon (Si) and germanium (Ge) are attractive anode materials for next generation batteries because they have significantly higher capacities compared with current graphite anodes. One of the challenges Si and Ge face during battery cycling is high volume expansion upon lithiation, which can be accommodated by nanostructuring. LIBs made using Si and Si-Ge type II clathrates exhibited superior reversible cycling performance. This high capacity and stability is due to the type II phase purity of the samples which is a unique feature of the synthetic method used in this study. During cycling, the anode will react with the electrolyte, forming a passivating solid electrolyte interphase (SEI) layer on the surface, which is crucial to stable battery function. The formation of this layer is influenced by the surface chemistry of the active material. Ge NWs with different surface passivations exhibited different battery performance and rate capability. One strategy used to improve the performance of nanostructured Si, is the addition of a surface coating layer. Si nanowires coated with an SiO[subscript x] shell examined using in situ transmission electron microscopy during battery cycling showed reduced volume expansion, at the expense of complete lithiation. When the nanowire is delithiated, pores are observed to form in the amorphized Si due to the SiO[subscript x] shell, which prevents the migration of vacancies formed during delithiation to the nanowire surface. To increase the performance of the LIB, both the anode and cathode capacities must increase. Prelithiation of the Si anode was crucial to improve the capacity and stability of battery cycling for both lithium iron phosphate and sulfur cathodes, and the prelithiation process used strongly influenced battery performance. In a full cell with a sulfur cathode, no sulfides were observed in the Si SEI layer, due to the use of a carbon interlayer. Si-S batteries fully consumed the lithium nitrate electrolyte additive during cycling, resulting in high levels of electrolyte degradation that contaminated the anode and reduced battery stabilityItem Silicon and germanium nanostructures : synthesis and in situ TEM study(2015-08) Lu, Xiaotang; Korgel, Brian Allan, 1969-; Ekerdt, John G; Chelikowsky, James R; MacDonald, Allan H; Yu, GuihuaA variety of chemical routes exist for a wide range of nanomaterials with tunable size, shape, composition and surface chemistry. Of these materials, silicon (Si) and germanium (Ge) nanomaterials have been some of the most challenging to synthesize. Solution-liquid-solid (SLS) growth of Si was studied using tin (Sn) as the seeding metal. Si nanorods with narrow diameters can be grown by the decomposition of trisilane in hot squalane in the presence of Sn nanocrystals. Photoluminescence could be obtained from the Si nanorods by thermal hydrosilylation passivation. This colloidal synthesis could be further simplified to a single-step reaction procedure by the in situ formation of Sn seed particles. In addition to trisilane as a Si source, isotetrasilane, neopentasilane and cyclohexasilane were studied for Si nanorod growth: all three reactants enabled nanorod formation at lower growth temperatures. A monophenylsilane (MPS) enhanced growth was discovered for supercritical fluid-liquid-solid (SFLS) growth of Ge nanowires that enables the Ge conversion of ~100%. A variety of metalorganic compounds were studied for replacing pre-synthesized metal nanoparticles to induce Ge nanowire growth. Si and Ge nanowires are some of the most promising anode materials in lithium ion batteries (LIBs) because of their high lithium storage capacity. However, the significant chemical and physical changes that occur during cycling hamper their practical uses. In situ transmission electron microscopy (TEM) techniques were conducted to observe and understand structural and interfacial changes of the Si and Ge nanowires during electrochemical cycling; and, therefore, resolving the problems with current anodes by materials modification. The in situ TEM experiments showed that the incorporation of Sn into Si nanowires can enhance their rate capability. But the enhanced Li diffusion leads to the premature pore formation in Si nanowires. Ge nanowires has been discovered the potential as sodium ion battery anodes after an initial activation with a lithiation step to amorphize the nanowires.