Browsing by Subject "Fault tolerance (Engineering)"
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Item A reconfiguration-based defect-tolerant design paradigm for nanotechnologies(2006) He, Chen; Jacome, Margarida F.Entering the nanometer era, a major challenge to current design method ologies and tools is how to effectively address the high defect densities pro jected for emerging nanotechnologies. To this end, in this dissertation we propose a reconfiguration-based defect-tolerant design paradigm for defect prone nanoelectronic technologies. In our paradigm, designs are mapped into a nanofabric comprised of reconfigurable regions, architected using a suitable hierarchy of design abstractions, so as to meet the target yield with best ex pected performance. The new design goal is thus to devise an appropriate structural/behavioral decomposition which improves scalability by constrain ing the defect mapping and reconfiguration process to small fabric regions, while meeting a desired probability of successful instantiation, i.e., yield. A key feature of our proposed nanofabric architecture is that it en ables the defect mapping and configuration tasks to be performed within the nanofabric itself, eliminating the costly per-chip offline processing. Specifically, we have devised a novel group testing method that can systematically identify defective components and/or connectivity in a fabric region. It enables the entire fabric to be tested and configured in a scalable way, using a relatively small number of easily configured triple-modular-redundancy (TMR) test tiles executing concurrently on different regions of the target nanofabric. Moreover, our proposed design paradigm offers a rich framework in which critical trade-offs among performance, yield, and complexity can be explored. The probabilistic nature of these tradeoffs has required us to in troduce a new class of ‘reliability-aware’ high-level synthesis (HLS) problems. In particular, rather than carefully optimizing a single (‘deterministic’) solu tion, as done in traditional HLS, our approach requires the joint synthesis and optimization of a sufficiently large family of alternative solutions, so as to achieve the specified target yield, with best-expected performance. We have developed a Reliability-Aware Synthesis framework for NANOfabrics (RAS NANO), aimed at systematically solving this new class of ‘reliability-aware’ HLS problem. It enables designers to effectively explore the complex prob abilistic design space associated with the new reconfiguration-based defect tolerant design paradigm.Item Statistical algorithms for circuit synthesis under process variation and high defect density(2007-12) Singh, Ashish Kumar, 1981-; Orshansky, MichaelAs the technology scales, there is a need to develop design and optimization algorithms under various scenarios of uncertainties. These uncertainties are introduced by process variation and impact both delay and leakage. For future technologies at the end of CMOS scaling, not only process variation but the device defect density is projected to be very high. Thus realizing error tolerant implementation of Boolean functions with minimal redundancy overhead remains a challenging task. The dissertation is concerned with the challenges of low-power and area digital circuit design under high parametric variability and high defect density. The technology mapping provides an ideal starting point for leakage reduction because of higher structural freedom in the choices of implementations. We first describe an algorithm for technology mapping for yield enhancement that explicitly takes parameter variability into account. We then show how leakage can be reduced by accounting for its dependence on the signal state, and develop a fast gain-based technology mapping algorithm. In some scenarios the state probabilities can not be precise point values but are modeled as an interval. We extended the notion of mean leakage to the worst case mean leakage which is defined as the sum of maximal mean leakage of circuit gates over the feasible probability realizations. The gain-based algorithm has been generalized to optimize this proxy leakage metric by casting the problem within the framework of robust dynamic programming. The testing is performed by selecting various instance probabilities for the primary inputs that are deviations from the point probabilities with respect to which a point probability based gain based mapper has been run. We obtain leakage improvement for certain test probabilities with the interval probability based over the point probability based mapper. Next, we present techniques based on coding theory for implementing Boolean functions in highly defective fabrics that allow us to tolerate errors to a certain degree. The novelty of this work is that the structure of Boolean functions is exploited to minimize the redundancy overhead. Finally we have proposed an efficient analysis approach for statistical timing, which can correctly propagate the slope in the path-based statistical timing analysis. The proposed algorithm can be scaled up to one million paths.