Browsing by Subject "FET"
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Item Chemical vapor sensing with novel coupled-channel field-effect transistors(2018-11-01) Lewis, Shannon Doane; Dodabalapur, Ananth, 1963-; Lee, Jack C; Bank, Seth; Shih, Chin-Kang; Vanden Bout, David AChemical vapor sensing has numerous practical applications. Many small polar organic molecules, from alcohols to explosives, are tested for in ambient atmosphere every day as part of security and air quality monitoring. However, many of these tests require expensive monitoring equipment. This work explores organic and inorganic oxide semiconductors as room-temperature low-cost chemical vapor sensors. Organic semiconductors have well-known chemical vapor sensing capabilities that arise from the grain boundaries and charge transport in their non-crystalline structure. However, organic semiconductors suffer from the bias stress effect in atmosphere and low mobilities. Inorganic oxide semiconductors also display sensitivity to polar vapor molecules and are transparent at visible wavelengths, which makes them of interest to the display industry. Coupling disordered semiconductors with silicon channels can produce the detection range of organic and inorganic oxide semiconductors combined with the stability of electrical characteristics of silicon semiconductor devices. This work discusses three different device geometries designed to allow organic and inorganic oxide semiconductors to influence the current in a complementary silicon semiconductor channel. The four-terminal device is a novel device geometry developed to function in a chemical memory mode that produces a one hundred-fold increase in silicon drain current in response to polar analyte vapor exposure. Thin film transistor (TFT) geometry relies on a silicon substrate to function as a bottom gate and processing platform. The bilayer device geometry also uses a silicon substrate as a bottom gate and processing platform, but then relies on the interaction of an inorganic oxide semiconductor and organic semiconductor in a planar heterojunction to produce a sensing event. The sensing mechanisms and responses for these devices are discussed in this work.Item Circuit design and device modeling of zinc-tin oxide TFTs(2011-05) Divakar, Kiran; Viswanathan, T. R., doctor of electrical engineering; Dodabalapur, Ananth, 1963-Amorphous Oxide Semiconductors (AOS) are widely being explored in the field of flexible and transparent electronics. In this thesis, solution processed zinc-tin oxide (ZTO) n-channel TFT based circuits are studied. Inverters, single stage amplifiers and ring oscillators are designed, fabricated and tested. 7-stage ring oscillators with output frequencies up to 106kHz and 5-stage ring oscillators with frequencies up to 75kHz are reported. A stable three stage op-amp with a buffered output is designed for a gain of 39.9dB with a unity gain frequency of 27.7kHz. A 7-stage ring oscillator with output frequency close to 1MHz is simulated and designed. The op-amp and the ring oscillator are ready to be fabricated and tested. An RPI model for a-Si, adapted to fit the ZTO device characteristics, is used for simulation. Development of a new model based on the physics behind charge transport in ZTO devices is explored. An expression for gate bias dependent mobility in ZTO devices is derived.Item Epitaxial germanium via Ge:C and its use in non-classical semiconductor devices(2015-12) Mantey, Jason Christopher; Banerjee, Sanjay; Lee, Jack C; Register, Leonard F; Akinwande, Deji; Ferreira, Paulo JThe microelectronics industry has been using Silicon (Si) as the primary material for complementary metal-oxide-semiconductor (CMOS) chip fabrication for more than six decades. Throughout this time, these CMOS devices have gotten exponentially smaller, faster, and cheaper. While new materials and fabrication processes have been slowly added over the years, the CMOS device of today is largely the same as it was decades ago. However, field-effect transistors (FETs) have now scaled so far that Si is approaching physical limits. Thus, new channel materials and new fundamental device structures are being investigated to replace traditional CMOS. Germanium is one of the prime candidates to replace Si in the FET channel, with its increased electron and hole mobilities compared to Si. Perhaps more importantly, it is compatible with the existing Si manufacturing techniques by epitaxially growing thin layers of Ge crystal on the starting Si wafer. Because these two crystals do not share a lattice constant, there will inevitably be crystal defects in the thin Ge layer that can be catastrophic for device functionality. Several approaches have been introduced to reduce defects, but most of them are wastefully thick (>1 um) or require complex manufacturing methods. In this work, we utilize an extremely thin (~10 nm) buffer layer of carbon-doped Ge (Ge:C) to grow Ge and SiGe layers for FET and virtual substrate applications with improved crystalline quality and reduced surface roughnesses. These thin Ge layers not only offer new pathways for MOSFETs, but can also be used in non-classical structures. Semiconductor nanowires (NWs) and tunnel-FETs (TFETs) are two of the most promising device architectures, and both can be used with Ge. This dissertation presents a simulated Si/Ge heterostructure interface TFET that can be fabricated on a virtual substrate made with the Ge:C buffer layer. Detailed analysis on device operation is given. Also in this work is the fabrication process for individually addressable Ge NW-FETs. The NWs offer excellent electrostatic gate control through reduced dimensions and offer another potential pathway for Ge in a post-CMOS world.