Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) integration. The mismatch of thermal expansion coefficients between the Cu via and Si can generate significant stresses in ...

A nanoindentation system was employed to characterize mechanical properties of silicon nanolines (SiNLs), which were fabricated by an anisotropic wet etching (AWE) process. The SiNLs had the linewidth ranging from 24 nm ...

Plasma damage to low k dielectric materials was investigated from a mechanistic point of view. Low k dielectric films were treated by plasma Ar, O-2, N-2/H-2, N-2 and H-2 in a standard RIE chamber and the damage was ...

Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with ...

The effect of line scaling on Cu grain structures has been investigated by using both plan-view and cross-sectional transmission electron microscopy (TEM) techniques. Cu damascene lines with three different line widths of ...

This paper combined experiments and simulation to investigate the grain size and cap layer effects on electromigration (EM) reliability of Cu interconnects. First the statistical distribution of EM lifetime and failure ...

In 3-D interconnect structures, process-induced thermal stresses around through silicon vias (TSVs) raise serious reliability issues such as silicon cracking and performance degradation of devices. In this study, the ...