Now showing items 1-6 of 6
Characterization Of Thermal Stresses And Plasticity In Through-Silicon Via Structures For Three-Dimensional Integration
Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) integration. The mismatch of thermal expansion coefficients between the Cu via and Si can generate significant stresses in ...
Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias
Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently threedimensional (3-D) integration with ...
Nanoindentation Of Si Nanostructures: Buckling And Friction At Nanoscales
A nanoindentation system was employed to characterize mechanical properties of silicon nanolines (SiNLs), which were fabricated by an anisotropic wet etching (AWE) process. The SiNLs had the linewidth ranging from 24 nm ...
Stress-Induced Delamination Of Through Silicon Via Structures
Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three-dimensional (3-D) integration with ...
Thermomechanical Characterization And Modeling For TSV Structures
Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with ...
Line Scaling Effect On Grain Structure For Cu Interconnects
The effect of line scaling on Cu grain structures has been investigated by using both plan-view and cross-sectional transmission electron microscopy (TEM) techniques. Cu damascene lines with three different line widths of ...