Learning-based architecture-level power modeling of CPUs

Date

2020-05-07

Authors

Ananda Kumar, Ajay Krishna

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Abstract

With the end of Dennard scaling, energy efficiency has become an important metric driving future processor architectures, particularly in the fields of mobile and embedded devices. To support rapid, power-aware design space exploration, it is important to accurately quantify the power consumption of the different micro-architectural components of processors early in the design flow and at a high level of abstraction. Existing CPU power models rely on either generic analytical power models or simple regression-based techniques that suffer from large inaccuracies. Recently proposed machine learning techniques for accurate power modeling still require slow RTL simulations or have only been demonstrated for fixed-function accelerators at higher levels. In this thesis, we present a novel approach that uses machine-learning to model cycle-accurate power consumption of programmable processors and their internal structures at a high micro-architectural level. Using only high-level information that can be obtained from micro-architecture simulations, we extract representative features and develop low-complexity learning formulations for different micro-architecture components that require a small number of gate-level simulations for training. We further present a hierarchical power model composition methodology to build power models for complete CPUs. Our composed models provide cycle-accurate and hierarchical power estimates down to sub-block granularity. We demonstrate the generality of our approach by modeling a simple in-order core as well as a complex superscalar out-of-order core. Results show that our hierarchically composed models for two RISC-V processor cores, RI5CY core from the PULP platform and Berkeley Out-of-Order Machine (BOOM), predicts cycle-by-cycle power consumption to within 2.2% and within 2.9% of a gate-level power estimation on average, respectively. In addition, our power model for the BOOM core, trained on micro-benchmarks, has an error rate of less than 3.6% when predicting cycle-by-cycle power consumption of a real-world application

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