Design techniques for ultra-low-power sensor interface circuits and systems in nano-scale CMOS technologies
In recent decades, the internet of things (IoT) has been sprout, resulting from the improvement of the circuit design and manufacturing techniques. Moreover, the emerging of 5G technologies further enhances its growth. Autonomous wireless sensors and their networks have been one of the most prevailing and important research topics for the past decades. Although researchers have been pushing the state-of-the-art of sensor readout to have higher and higher power and area efficiency, the results turn out to be insufficient to meet the modern requirements, especially considering the number of sensors is dramatically growing and a large portion of them are battery-less devices. Thus, maintaining a high resolution and low noise while achieving a high power and area efficiency has been one of the major challenges for sensor readout circuit designs in recent years. This thesis proposes several novel power- and area-saving techniques for the fundamental building blocks: 1) the inverter-stacking technique; and 2) the tail-less inverter-stacking technique for LNA; 3) the CT-SAR-assisted two-step SAR ADC with kT/C noise attenuated. The first work presents a highly power-efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves 6-time current reuse, thereby significantly boosting the transconductance and lowering noise but without increasing the current consumption. A novel biasing scheme is devised to ensure robust operation under 1 V supply. A prototype in 180 nm CMOS has 5.5 μV [subscript rms] noise within 10 kHz BW while consuming only 0.25 μW power, leading to a noise efficiency factor (NEF) of 1.07, which is the best among reported amplifiers. The second work presents a low-noise capacitively-coupled instrumentation amplifier, featuring the better-than-bipolar power efficiency. The tail-less structure removes the tail current source, reducing the supply voltage to be 0.6 V, and thus significantly reducing the power consumption. Compared with other recently reported front-end amplifiers, it achieves the best trade-off between power consumption and input-referred noise (IRN). AC-coupling and current mode biased are employed to enhance its PVT robustness.f In addition, several other design techniques are used, including AC coupling with optimized gain allocation-based ripple reduction, CM-pre-filtering based CMRR enhancement. The prototype fabricated in 180-nm CMOS process achieved an integrated input-referred rms noise of 1.38 μV [subscript rms] within an 8-kHz bandwidth. With one global 0.6-V supply voltage, the prototype consumes 2.7-μW of total power, leading to a PEF of 0.96. The peak CMRR and PSRR are measured to be 84 dB and 78 dB, respectively, which validates the performance enhancement techniques with the pseudo-differential input stage. The third work presents a two-step analog-to-digital converter (ADC) that operates its 1st-stage successive approximation register (SAR) ADC in the continuous-time (CT) domain. It avoids the front-end sample-and-hold (S/H) circuit and its associated sampling noise. Hence, the proposed ADC allows the input capacitor size to be substantially reduced without incurring large sampling noise penalty. With input AC coupling, the 1st-stage CT SAR can simultaneously perform input tracking and SAR quantization. Its conversion error is minimized by accelerating the SAR speed and providing redundancy. A floating inverter-based (FIB) dynamic amplifier (DA) is used as the inter-stage amplifier and acts as a low-pass filter for the 1st-stage residue. To verify the proposed techniques, a 13-bit prototype ADC is built in 40nm CMOS process. Its input capacitor is only 120 fF, which is over 20 times smaller than what would be needed in a classic Nyquist ADC with the S/H circuit. Operating at 2 MS/s, it achieves 72-dB SNDR at the Nyquist rate while consuming only 25 μW of power and 0.01 mm² of area.