Simultaneous statistical delay and slew optimization for interconnect pipelines

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dc.contributor.advisorPan, David Z.
dc.creatorHavlir, Andrew Michael
dc.date.accessioned2023-10-06T23:57:24Z
dc.date.available2023-10-06T23:57:24Z
dc.date.issued2005-12-24
dc.description.abstractProcess variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the delay distribution of an interconnect pipeline stage and the slew distributions of all the nets in the circuit. Also, a buffer sizing and re-placement algorithm is developed to minimize the area of interconnect pipelines while meeting the delay and slew constraints. Experiments show that ignoring location dependent variation can cause timing yield loss of 8.8% in a delay limited circuit. Furthermore, the area of the circuit can be improved by over 10% when the location dependent variation and residual random variation are understood and separated. Lastly, experiment results show that sizing alone is not sufficient to optimize interconnect pipelines with location dependent variation. Under equivalent area, a circuit optimized with only sizing changes may violate the slew constraint on over 50% of the netsen_US
dc.description.departmentElectrical and Computer Engineeringen_US
dc.format.mediumelectronicen_US
dc.identifier.urihttps://hdl.handle.net/2152/121889
dc.identifier.urihttp://dx.doi.org/10.26153/tsw/48707
dc.language.isoengen_US
dc.relation.ispartofUT Electronic Theses and Dissertationsen_US
dc.rightsCopyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en_US
dc.rights.restrictionRestricteden_US
dc.subjectSlew optimizationen_US
dc.subjectProcess variationen_US
dc.subjectInterconnect pipelinesen_US
dc.subjectModel validationen_US
dc.titleSimultaneous statistical delay and slew optimization for interconnect pipelinesen_US
dc.typeThesisen_US
dc.type.genreThesisen_US
thesis.degree.departmentElectrical and Computer Engineeringen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.grantorUniversity of Texas at Austinen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Science in Engineeringen_US

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